Information

43.4.3 DSPI baud rate and clock delay generation
The SCK frequency and the delay values for serial transfer are generated by dividing the
system clock frequency by a prescaler and a scaler with the option for doubling the baud
rate. The following figure shows conceptually how the SCK signal is generated.
System Clock
Prescaler
1
Scaler
1+DBR
SCK
Figure 43-48. Communications clock prescalers and scalers
43.4.3.1 Baud rate generator
The baud rate is the frequency of the SCK. The system clock is divided by a prescaler
(PBR) and scaler (BR) to produce SCK with the possibility of halving the scaler division.
The DBR, PBR, and BR fields in the CTARs select the frequency of SCK by the formula
in the BR field description. The following table shows an example of how to compute the
baud rate.
Table 43-54. Baud rate computation example
f
SYS
PBR Prescaler BR Scaler DBR Baud rate
100 MHz 0b00 2 0b0000 2 0 25 Mb/s
20 MHz 0b00 2 0b0000 2 1 10 Mb/s
NOTE
The clock frequencies mentioned in the preceding table are
given as an example. Refer to the clocking chapter for the
frequency used to drive this module in the device.
43.4.3.2 PCS to SCK Delay (t
CSC
)
The PCS to SCK delay is the length of time from assertion of the PCS signal to the first
SCK edge. See Figure 43-49 for an illustration of the PCS to SCK delay. The PCSSCK
and CSSCK fields in the CTARx registers select the PCS to SCK delay by the formula in
the CSSCK field description. The following table shows an example of how to compute
the PCS to SCK delay.
Table 43-55. PCS to SCK delay computation example
f
SYS
PCSSCK Prescaler CSSCK Scaler PCS to SCK Delay
100 MHz 0b01 3 0b0100 32 0.96 μs
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 989