Information

When in Non-Continuous Clock mode the t
DT
delay is configured according to the
equation specified in the CTAR[DT] bitfield description. When in Continuous Clock
mode, the delay is fixed at 1 SCK period.
43.4.4 Transfer formats
The SPI serial communication is controlled by the Serial Communications Clock (SCK)
signal and the PCS signals. The SCK signal provided by the master device synchronizes
shifting and sampling of the data on the SIN and SOUT pins. The PCS signals serve as
enable signals for the slave devices.
In Master mode, the CPOL and CPHA bits in the Clock and Transfer Attributes Registers
(CTARn) select the polarity and phase of the serial clock, SCK.
• CPOL - Selects the idle state polarity of the SCK
• CPHA - Selects if the data on SOUT is valid before or on the first SCK edge
Even though the bus slave does not control the SCK signal, in Slave mode these values
must be identical to the master device settings to ensure proper transmission. In SPI Slave
mode, only CTAR0 is used.
The DSPI supports four different transfer formats:
• Classic SPI with CPHA=0
• Classic SPI with CPHA=1
• Modified Transfer Format with CPHA = 0
• Modified Transfer Format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with
peripherals that require longer setup times. The DSPI can sample the incoming data later
than halfway through the cycle to give the peripheral more setup time. The MTFE bit in
the MCR selects between Classic SPI Format and Modified Transfer Format.
In the SPI configurations, the DSPI provides the option of keeping the PCS signals
asserted between frames. See Continuous Selection Format for details.
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 991