Information

PCS
Master SIN
tCSC
=
P
C
S
to SCK del ay
t
ASC
=
After SCK delay
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
t
CSC
t
ASC
t
CSC
Figure 43-52. Example of continuous transfer (CPHA=1, CONT=1)
When using DSPI with continuous selection follow these rules:
• All transmit commands must have the same PCSn bits programming.
• The CTARs, selected by transmit commands, must be programmed with the same
transfer attributes. Only FMSZ field can be programmed differently in these CTARs.
• When transmitting multiple frames in this mode, the user software must ensure that
the last frame has the PUSHR[CONT] bit deasserted in Master mode and the user
software must provide sufficient frames in the TX_FIFO to be sent out in Slave mode
and the master deasserts the PCSn at end of transmission of the last frame.
• The PUSHR[CONT] / DSICR0[DCONT] bits must be deasserted before asserting
MCR[HALT] bit in master mode. This will make sure that the PCSn signals are
deasserted. Asserting MCR[HALT] bit during continuous transfer will cause the
PCSn signals to remain asserted and hence Slave Device cannot transition from
Running to Stopped state.
NOTE
User must fill the TX FIFO with the number of entries that will
be concatenated together under one PCS assertion for both
master and slave before the TX FIFO becomes empty.
When operating in Slave mode, ensure that when the last entry
in the TX FIFO is completely transmitted, that is, the
corresponding TCF flag is asserted and TXFIFO is empty, the
slave is deselected for any further serial communication;
otherwise, an underflow error occurs.
Chapter 43 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 995