Information

43.4.5 Continuous Serial Communications Clock

The DSPI provides the option of generating a Continuous SCK signal for slave

peripherals that require a continuous clock.

Continuous SCK is enabled by setting the CONT_SCKE bit in the MCR. Enabling this

bit generates the Continuous SCK regardless of the MCR[HALT] bit status. Continuous

SCK is valid in all configurations.

Continuous SCK is only supported for CPHA=1. Clearing CPHA is ignored if the

CONT_SCKE bit is set. Continuous SCK is supported for Modified Transfer Format.

Clock and transfer attributes for the Continuous SCK mode are set according to the

following rules:

• When the DSPI is in SPI configuration, CTAR0 is used initially. At the start of each

SPI frame transfer, the CTAR specified by the CTAS for the frame is used.

• In all configurations, the currently selected CTAR remains in use until the start of a

frame with a different CTAR specified, or the Continuous SCK mode is terminated.

It is recommended to keep the baud rate the same while using the Continuous SCK.

Switching clock polarity between frames while using Continuous SCK can cause errors

in the transfer. Continuous SCK operation is not guaranteed if the DSPI is put into the

External Stop mode or Module Disable mode.

Enabling Continuous SCK disables the PCS to SCK delay and the Delay after Transfer

) is fixed to one SCK cycle. The following figure is the timing diagram for

Continuous SCK format with Continuous Selection disabled.

NOTE

In Continuous SCK mode, for the SPI transfer CTAR0 should

always be used, and the TX FIFO must be cleared using the

MCR[CLR_TXF] field before initiating transfer.

Functional description

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

996 Freescale Semiconductor, Inc.