Information

43.4.6 Slave Mode Operation Constraints
Slave mode logic shift register is buffered. This allows data streaming operation, when
the DSPI is permanently selected and data is shifted in with a constant rate.
The transmit data is transferred at second SCK clock edge of the each frame to the shift
register if the SS signal is asserted and any time when transmit data is ready and SS
signal is negated.
Received data is transferred to the receive buffer at last SCK edge of each frame, defined
by frame size programmed to the CTAR0/1 register. Then the data from the buffer is
transferred to the RXFIFO or DDR register.
If the SS negates before that last SCK edge, the data from shift register is lost.
43.4.7 Interrupts/DMA requests
The DSPI has several conditions that can generate only interrupt requests and two
conditions that can generate interrupt or DMA requests. The following table lists these
conditions.
Table 43-58. Interrupt and DMA request conditions
Condition Flag Interrupt DMA
End of Queue (EOQ) EOQF Yes -
TX FIFO Fill TFFF Yes Yes
Transfer Complete TCF Yes -
TX FIFO Underflow TFUF Yes -
RX FIFO Drain RFDF Yes Yes
RX FIFO Overflow RFOF Yes -
Each condition has a flag bit in the DSPI Status Register (SR) and a Request Enable bit in
the DSPI DMA/Interrupt Request Select and Enable Register (RSER). Certain flags (as
shown in above table) generate interrupt requests or DMA requests depending on
configuration of DSPI_RSER register.
The DSPI module also provides a global interrupt request line, which is asserted when
any of individual interrupt requests lines is asserted.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
998 Freescale Semiconductor, Inc.