Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 32-Bit 50 MHz I/O number 40

K20P64M50SF0

K20 Sub-Family

Supports the following:

MK20DN32VLH5, MK20DX32VLH5,

MK20DN64VLH5, MK20DX64VLH5,

MK20DN128VLH5, MK20DX128VLH5,

MK20DN32VMP5, MK20DX32VMP5,

MK20DN64VMP5, MK20DX64VMP5,

MK20DN128VMP5, MK20DX128VMP5

Features

•

Operating Characteristics

–

Voltage range: 1.71 to 3.6 V

– Flash write voltage range: 1.71 to 3.6 V

– Temperature range (ambient): -40 to 105°C

•

Performance

– Up to 50 MHz ARM Cortex-M4 core with DSP

instructions delivering 1.25 Dhrystone MIPS per

MHz

•

Memories and memory interfaces

– Up to 128 KB program flash.

– Up to 32 KB FlexNVM on FlexMemory devices

– 2 KB FlexRAM on FlexMemory devices

– Up to 16 KB RAM

– Serial programming interface (EzPort)

•

Clocks

– 3 to 32 MHz crystal oscillator

– 32 kHz crystal oscillator

– Multi-purpose clock generator

•

System peripherals

– Multiple low-power modes to provide power

optimization based on application requirements

– 4-channel DMA controller, supporting up to 41

request sources

– External watchdog monitor

– Software watchdog

– Low-leakage wakeup unit

•

Security and integrity modules

– Hardware CRC module to support fast cyclic

redundancy checks

– 128-bit unique identification (ID) number per chip

•

Analog modules

– 16-bit SAR ADC

– Two analog comparators (CMP) containing a 6-bit

DAC and programmable reference input

– Voltage reference

•

Timers

– Programmable delay block

– Eight-channel motor control/general purpose/PWM

timer

– Two-channel quadrature decoder/general purpose

timer

– Periodic interrupt timers

– 16-bit low-power timer

– Carrier modulator transmitter

– Real-time clock

•

Communication interfaces

– USB full-/low-speed On-the-Go controller with on-

chip transceiver

– SPI module

– I2C module

– Three UART modules

– I2S module

Freescale Semiconductor

Document Number: K20P64M50SF0

Data Sheet: Technical Data

Rev. 4 5/2012

Freescale reserves the right to change the detail specifications as may be

required to permit improvements in the design of its products.

Summary of content (62 pages)

PAGE 1
Freescale Semiconductor Data Sheet: Technical Data Document Number: K20P64M50SF0 Rev. 4 5/2012 K20P64M50SF0 K20 Sub-Family Supports the following: MK20DN32VLH5, MK20DX32VLH5, MK20DN64VLH5, MK20DX64VLH5, MK20DN128VLH5, MK20DX128VLH5, MK20DN32VMP5, MK20DX32VMP5, MK20DN64VMP5, MK20DX64VMP5, MK20DN128VMP5, MK20DX128VMP5 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.
PAGE 2
Table of Contents 1 Ordering parts...........................................................................3 5.4.1 Thermal operating requirements...........................21 1.1 Determining valid orderable parts......................................3 5.4.2 Thermal attributes.................................................21 2 Part identification......................................................................3 6 Peripheral operating requirements and behaviors....................22 2.
PAGE 3
Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: PK20 and MK20 . 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.
PAGE 4
Terminology and guidelines Field Description Values FFF Program flash memory size • • • • • • 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • • • • • • • • • • • • • FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) LK = 80 LQF
PAGE 5
Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 Example This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 3.
PAGE 6
Terminology and guidelines 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. — Max. 7 Unit pF 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.
PAGE 7
Terminology and guidelines 3.6 Relationship between ratings and operating requirements e Op ing rat r ( ng ati in. t (m ) n. mi rat e Op ing ) t (m e ir qu re n me ing rat e Op ax .) e ir qu re n me ing rat e Op ng ati ax (m .
PAGE 8
Terminology and guidelines 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit µA 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 3.
PAGE 9
Ratings 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.
PAGE 10
General Symbol IDD Description Digital supply current Min. Max. Unit — 155 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 VDD + 0.3 V VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V Maximum current single pin limit (applies to all port pins) –25 25 mA ID VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V VUSB_DP USB_DP input voltage –0.3 3.63 V VUSB_DM USB_DM input voltage –0.3 3.63 V VREGIN USB regulator input –0.3 6.
PAGE 11
General 5.2 Nonswitching electrical specifications 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V 1.71 3.6 V • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V • 2.7 V ≤ VDD ≤ 3.6 V — 0.
PAGE 12
General 5.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold — high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds — high range 1 VLVW1H • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV=10) 2.82 2.90 2.
PAGE 13
General 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Description Min. Max. Unit • 2.7 V ≤ VDD ≤ 3.6 V, IOH = - 9 mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA VDD – 0.5 — V • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA VDD – 0.5 — V — 100 mA • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9 mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA — 0.5 V • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA — 0.
PAGE 14
General Table 5. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. • VLLS0 → RUN • VLLS1 → RUN • VLLS2 → RUN • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN Min. Max. Unit Notes — 300 μs 1 — 130 μs — 130 μs — 70 μs — 70 μs — 6 μs — 5.2 μs — 5.2 μs 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.2.
PAGE 15
General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 867 — μA 6 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 1.1 — mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V — 509 — μA 8 IDD_STOP Stop mode current at 3.
PAGE 16
General Table 6. Power consumption operating behaviors (continued) Symbol IDD_VLLS0 Description • @ 70°C • @ 105°C Max. Unit — 0.176 0.859 μA — 2.2 13.1 μA — 13 23.9 μA — 0.19 0.22 μA — 0.49 0.64 μA — 2.2 3.2 μA Notes Average current with RTC and 32kHz disabled at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C IDD_VBAT Typ. Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled • @ –40 to 25°C IDD_VBAT Min.
PAGE 17
General • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFL Figure 2. Run mode supply current vs. core frequency K20 Sub-Family Data Sheet, Rev. 4 5/2012. Freescale Semiconductor, Inc.
PAGE 18
General Figure 3. VLPR mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 64LQFP Symbol Description Frequency band (MHz) Typ. Unit Notes 1,2 VRE1 Radiated emissions voltage, band 1 0.15–50 19 dBμV VRE2 Radiated emissions voltage, band 2 50–150 21 dBμV VRE3 Radiated emissions voltage, band 3 150–500 19 dBμV VRE4 Radiated emissions voltage, band 4 500–1000 11 dBμV IEC level 0.
PAGE 19
General emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 48 MHz, fBUS = 48MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 5.2.
PAGE 20
General Table 9. Device clock specifications (continued) Symbol Description Min. Max. Unit fFLASH Flash clock — 1 MHz fERCLK External reference clock — 16 MHz LPTMR clock — 25 MHz LPTMR external reference clock — 16 MHz fI2S_MCLK I2S master clock — 12.5 MHz fI2S_BCLK I2S bit clock — 4 MHz fLPTMR_pin fLPTMR_ERCLK Notes 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 5.3.
PAGE 21
General Table 10. General switching specifications (continued) Symbol Description Min. Max. Unit Notes Port rise and fall time (low drive strength) 5 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 12 ns • 2.7 ≤ VDD ≤ 3.6V — 6 ns • 1.71 ≤ VDD ≤ 2.7V — 36 ns • 2.7 ≤ VDD ≤ 3.6V — 24 ns • Slew enabled 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized.
PAGE 22
Peripheral operating requirements and behaviors Board type Symbol Description 64 LQFP Unit Notes Single-layer (1s) RθJMA Thermal 90 resistance, junction to ambient (200 ft./ min. air speed) 53 °C/W 1,3 Four-layer (2s2p) RθJMA Thermal 51 resistance, junction to ambient (200 ft./ min.
PAGE 23
Peripheral operating requirements and behaviors 6.1.1 JTAG electricals Table 12. JTAG voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 5.
PAGE 24
Peripheral operating requirements and behaviors TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 5. Boundary scan (JTAG) timing TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 6. Test Access Port timing K20 Sub-Family Data Sheet, Rev. 4 5/2012. 24 Freescale Semiconductor, Inc.
PAGE 25
Peripheral operating requirements and behaviors TCLK J14 J13 TRST Figure 7. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules 6.3.1 MCG specifications Table 13. MCG specifications Symbol Description Min. Typ. Max. Unit — 32.768 — kHz 31.25 — 39.0625 kHz Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM — ± 0.3 ± 0.
PAGE 26
Peripheral operating requirements and behaviors Table 13. MCG specifications (continued) Symbol ffll_ref fdco Description FLL reference frequency range DCO output frequency range Low range (DRS=00) Min. Typ. Max. Unit 31.25 — 39.0625 kHz 20 20.97 25 MHz 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz — 23.99 — MHz — 47.97 — MHz — 71.99 — MHz — 95.98 — MHz — 180 — — 150 — — — 1 ms 48.0 — 100 MHz — 1060 — µA — 600 — µA 2.0 — 4.
PAGE 27
Peripheral operating requirements and behaviors Table 13. MCG specifications (continued) Symbol Description Min. Jacc_pll PLL accumulated jitter over 1µs (RMS) Typ. Max. Unit Notes 8 • fvco = 48 MHz — 1350 — ps • fvco = 100 MHz — 600 — ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 9 1.
PAGE 28
Peripheral operating requirements and behaviors Table 14. Oscillator DC electrical specifications (continued) Symbol Description Min. IDDOSC Supply current — high gain mode (HGO=1) Typ. Max. Unit Notes 1 • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.
PAGE 29
Peripheral operating requirements and behaviors 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 Symbol Oscillator frequency specifications Table 15. Oscillator frequency specifications Description Min. Typ. Max.
PAGE 30
Peripheral operating requirements and behaviors Table 16. 32kHz oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Cpara Parasitical capacitance of EXTAL32 and XTAL32 — 5 7 pF Vpp1 Peak-to-peak amplitude of oscillation — 0.6 — V 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.
PAGE 31
Peripheral operating requirements and behaviors 6.4.1.2 Symbol Flash timing specifications — commands Table 19. Flash command timing specifications Description Min. Typ. Max. Unit Notes Read 1s Block execution time trd1blk32k • 32 KB data flash — — 0.5 ms trd1blk128k • 128 KB program flash — — 1.
PAGE 32
Peripheral operating requirements and behaviors Table 19. Flash command timing specifications (continued) Symbol Description Min. Typ. Max.
PAGE 33
Peripheral operating requirements and behaviors Table 21. NVM reliability specifications (continued) Symbol Description tnvmretd1k Data retention after up to 1 K cycles nnvmcycd Cycling endurance Min. Typ.1 Max.
PAGE 34
Peripheral operating requirements and behaviors • EEPROM — allocated FlexNVM based on DEPART; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • nnvmcycd — data flash cycling endurance (the following graph assumes 10,000 cycles) Figure 8. EEPROM backup writes to FlexRAM 6.4.2 EzPort Switching Specifications Table 22.
PAGE 35
Peripheral operating requirements and behaviors Table 22. EzPort switching specifications (continued) Num Description Min. Max.
PAGE 36
Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit ADC operating conditions Table 23. 16-bit ADC operating conditions Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.
PAGE 37
Peripheral operating requirements and behaviors Table 23. 16-bit ADC operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate 16 bit modes Typ.1 Min. Max. Unit Notes 5 No ADC hardware averaging 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2.
PAGE 38
Peripheral operating requirements and behaviors Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol fADACK Description ADC asynchronous clock source Sample Time TUE DNL INL EFS Conditions1 Min. Typ.2 Max. Unit Notes • ADLPC=1, ADHSC=0 1.2 2.4 3.9 MHz • ADLPC=1, ADHSC=1 3.0 4.0 7.3 MHz tADACK = 1/ fADACK • ADLPC=0, ADHSC=0 2.4 5.2 6.1 MHz • ADLPC=0, ADHSC=1 4.4 6.2 9.
PAGE 39
Peripheral operating requirements and behaviors Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol SFDR Description Conditions1 Spurious free dynamic range 16 bit differential mode • Avg=32 16 bit single-ended mode • Avg=32 EIL Min. Typ.2 Max. Unit Notes 7 82 95 — dB 78 90 — dB Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope –40°C to 105°C — 1.
PAGE 40
Peripheral operating requirements and behaviors Figure 11. Typical ENOB vs. ADC_CLK for 16-bit differential mode Figure 12. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode K20 Sub-Family Data Sheet, Rev. 4 5/2012. 40 Freescale Semiconductor, Inc.
PAGE 41
Peripheral operating requirements and behaviors 6.6.2 CMP and 6-bit DAC electrical specifications Table 25. Comparator and 6-bit DAC electrical specifications Symbol VDD Description Min. Typ. Max. Unit Supply voltage 1.71 — 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA VAIN Analog input voltage VSS – 0.
PAGE 42
Peripheral operating requirements and behaviors 0.08 0.07 0.06 HYSTCTR Setting CM P Hystereris (V) 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K20 Sub-Family Data Sheet, Rev. 4 5/2012. 42 Freescale Semiconductor, Inc.
PAGE 43
Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP P Hystereris (V) 0.12 HYSTCTR Setting 0.1 00 01 0 08 0.08 10 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 Vin level (V) 1.9 2.2 2.5 2.8 3.1 Figure 14. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.6.3 Voltage reference electrical specifications Table 26. VREF full-range operating requirements Symbol Description Min. Max. Unit Supply voltage 1.71 3.
PAGE 44
Peripheral operating requirements and behaviors Table 27. VREF full-range operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output — factory trim 1.1584 — 1.2376 V Vout Voltage reference output — user trim 1.193 — 1.197 V Vstep Voltage reference trim step — 0.
PAGE 45
Peripheral operating requirements and behaviors 6.8.1 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org. 6.8.2 USB DCD electrical specifications Table 30. USB DCD electrical specifications Symbol Description Min. Typ. Max. Unit VDP_SRC USB_DP source voltage (up to 250 μA) 0.5 — 0.7 V Threshold voltage for logic high 0.
PAGE 46
Peripheral operating requirements and behaviors Table 31. USB VREG electrical specifications (continued) Symbol Description Min. Typ.1 Max. Unit COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA Notes 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2.
PAGE 47
Peripheral operating requirements and behaviors DSPI_PCSn DS3 DS1 DS2 DS4 DSPI_SCK DS8 DS7 (CPOL=0) DSPI_SIN Data First data Last data DS5 DSPI_SOUT DS6 First data Data Last data Figure 15. DSPI classic SPI timing — master mode Table 33. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Min. Max. Unit 2.7 3.6 V 12.
PAGE 48
Peripheral operating requirements and behaviors 6.8.5 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices.
PAGE 49
Peripheral operating requirements and behaviors Table 35. Slave mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit 1.71 3.6 V — 6.25 MHz 8 x tBUS — ns (tSCK/2) - 4 (tSCK/2) + 4 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid — 24 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 3.
PAGE 50
Peripheral operating requirements and behaviors 6.8.8 I2S/SAI Switching Specifications This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] is 0, RCR4[FSP] is 0).
PAGE 51
Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 19. I2S/SAI timing — master modes Table 37. I2S/SAI slave mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.
PAGE 52
Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 20. I2S/SAI timing — slave modes 6.8.8.2 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 38.
PAGE 53
Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 21. I2S/SAI timing — master modes Table 39. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.
PAGE 54
Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 22. I2S/SAI timing — slave modes 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 40. TSI electrical specifications Symbol Description Min. Typ. Max. Unit VDDTSI Operating voltage 1.71 — 3.
PAGE 55
Dimensions Table 40. TSI electrical specifications (continued) Symbol Description TCon20 ITSI_RUN ITSI_LP Min. Typ. Max. Unit Notes Response time @ 20 pF 8 15 25 μs 12 Current added in run mode — 55 — μA Low power mode current adder — 1.3 2.5 μA 13 1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. REFCHRG = 2, EXTCHRG=0. 4. REFCHRG = 0, EXTCHRG = 10. 5. VDD = 3.0 V.
PAGE 56
Pinout 8 Pinout 8.1 K20 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.
PAGE 57
Pinout 64 64 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 E5 24 PTA2 JTAG_TDO/ TSI0_CH3 TRACE_SWO/ EZP_DO PTA2 UART0_TX D5 25 PTA3 JTAG_TMS/ SWD_DIO TSI0_CH4 PTA3 UART0_RTS_ FTM0_CH0 b G5 26 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5 PTA4/ LLWU_P3 F5 27 PTA5 DISABLED PTA5 H6 28 PTA12 DISABLED G6 29 PTA13/ LLWU_P4 DISABLED G7 30 VDD VDD VDD H7 31 VSS VSS VSS H8 32 PTA18 EXTAL0 G8 33 PTA19 F8 34 F7 ALT4 ALT5 ALT6 FTM0_CH7 EzPort JTAG_TDO/ EZP_DO
PAGE 58
Pinout 64 64 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 B8 49 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 CMP1_OUT A8 50 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 CMP0_OUT A7 51 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT PDB0_EXTRG I2S0_RX_ BCLK B6 52 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_ OUT A6 53 PTC8 CMP0_IN2 CMP0_IN2 PTC8 I2S0_MCLK B5 54 PTC9 CMP0_IN3 CMP0_I
PAGE 59
PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout ADC0_DP0 9 40 PTB17 ADC0_DM0 10 39 PTB16 ADC0_DP3 11 38 PTB3 ADC0_DM3 12 37 PTB2 VDDA 13 36 PTB1 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 RESET_b VSSA 16 33 PTA19 32 PTB18 PTA18 41 31 8 VSS VREGIN 30 PTB19 VDD 42 29 7 PTA13/LLWU_P
PAGE 60
Revision History A B 1 2 3 4 5 6 PTE0 PTD7 PTD4/ LLWU_P14 PTD1 PTC11/ LLWU_P11 PTC8 PTD3 PTC10 PTC9 PTC7 VSS VDD PTD6/ PTE1/ LLWU_P0 LLWU_P15 PTD2/ PTD0/ LLWU_P13 LLWU_P12 7 8 PTC6/ PTC5/ LLWU_P10 LLWU_P9 A PTC2 PTC4/ LLWU_P8 B PTC1/ LLWU_P6 PTB19 PTC3/ LLWU_P7 C C PTD5 D USB0_DM VREGIN PTA0 PTA1 PTA3 PTB18 PTB17 PTC0 D E USB0_DP VOUT33 VSS VDD PTA2 PTB16 PTB2 PTB3 E F ADC0_DM0 ADC0_DM3 VSSA VDDA PTA5 PTB1 PTB0/ LLWU_P5 RESET_b F G ADC0_DP0 A
PAGE 61
Revision History Table 41. Revision History (continued) Rev. No. Date 4 5/2012 Substantial Changes • For the "32kHz oscillator frequency specifications", added specifications for an externally driven clock. • Renamed section "Flash current and power specfications" to section "Flash high voltage current behaviors" and improved the specifications. • For the "VREF full-range operating behaviors" table, removed the Ac (aging coefficient) specification.
PAGE 62
How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.