Information

Table 9. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
f
FLASH
Flash clock — 1 MHz
f
ERCLK
External reference clock — 16 MHz
f
LPTMR_pin
LPTMR clock — 25 MHz
f
LPTMR_ERCLK
LPTMR external reference clock — 16 MHz
f
I2S_MCLK
I2S master clock — 12.5 MHz
f
I2S_BCLK
I2S bit clock — 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, and I
2
C signals.
Table 10. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50 — ns 3
External reset pulse width (digital glitch filter disabled) 100 — ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 — Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ V
DD
≤ 2.7V
• 2.7 ≤ V
DD
≤ 3.6V
• Slew enabled
• 1.71 ≤ V
DD
≤ 2.7V
• 2.7 ≤ V
DD
≤ 3.6V
—
—
—
—
13
7
36
24
ns
ns
ns
ns
4
Table continues on the next page...
General
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
20 Freescale Semiconductor, Inc.