Information

6.1.1 JTAG electricals
Table 12. JTAG voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 2.7 5.5 V
J1 TCLK frequency of operation
• JTAG
• CJTAG
—
—
10
5
MHz
J2 TCLK cycle period 1/J1 — ns
J3 TCLK clock pulse width
• JTAG
• CJTAG
100
200
—
—
ns
ns
ns
J4 TCLK rise and fall times — 1 ns
J5 TMS input data setup time to TCLK rise
• JTAG
• CJTAG
53
112
—
—
ns
J6 TDI input data setup time to TCLK rise 8 — ns
J7 TMS input data hold time after TCLK rise
• JTAG
• CJTAG
3.4
3.4
—
—
ns
J8 TDI input data hold time after TCLK rise 3.4 — ns
J9 TCLK low to TMS data valid
• JTAG
• CJTAG
—
—
48
85
ns
J10 TCLK low to TDO data valid — 48 ns
J11
Output data hold/invalid time after clock edge
1
— 3 ns
1. They are common for JTAG and CJTAG. Input transition = 1 ns and Output load = 50pf
J2
J3 J3
J4 J4
TCLK (input)
Figure 4. Test clock input timing
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc. 23