Information
64
MAP
BGA
64
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
E5 24 PTA2 JTAG_TDO/
TRACE_SWO/
EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SWO
EZP_DO
D5 25 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RTS_
b
FTM0_CH0 JTAG_TMS/
SWD_DIO
G5 26 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
F5 27 PTA5 DISABLED PTA5 USB_CLKIN FTM0_CH2 I2S0_TX_
BCLK
JTAG_TRST_
b
H6 28 PTA12 DISABLED PTA12 FTM1_CH0 I2S0_TXD0 FTM1_QD_
PHA
G6 29 PTA13/
LLWU_P4
DISABLED PTA13/
LLWU_P4
FTM1_CH1 I2S0_TX_FS FTM1_QD_
PHB
G7 30 VDD VDD VDD
H7 31 VSS VSS VSS
H8 32 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0
G8 33 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_
ALT1
F8 34 RESET_b RESET_b RESET_b
F7 35 PTB0/
LLWU_P5
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
F6 36 PTB1 ADC0_SE9/
TSI0_CH6
ADC0_SE9/
TSI0_CH6
PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
PHB
E7 37 PTB2 ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2 I2C0_SCL UART0_RTS_
b
FTM0_FLT3
E8 38 PTB3 ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
PTB3 I2C0_SDA UART0_CTS_
b/
UART0_COL_
b
FTM0_FLT0
E6 39 PTB16 TSI0_CH9 TSI0_CH9 PTB16 UART0_RX EWM_IN
D7 40 PTB17 TSI0_CH10 TSI0_CH10 PTB17 UART0_TX EWM_OUT_b
D6 41 PTB18 TSI0_CH11 TSI0_CH11 PTB18 I2S0_TX_
BCLK
C7 42 PTB19 TSI0_CH12 TSI0_CH12 PTB19 I2S0_TX_FS
D8 43 PTC0 ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
PTC0 SPI0_PCS4 PDB0_EXTRG
C6 44 PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3 UART1_RTS_
b
FTM0_CH0 I2S0_TXD0
B7 45 PTC2 ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2 SPI0_PCS2 UART1_CTS_
b
FTM0_CH1 I2S0_TX_FS
C8 46 PTC3/
LLWU_P7
CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 I2S0_TX_
BCLK
E3 47 VSS VSS VSS
E4 48 VDD VDD VDD
Pinout
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc. 57