Information

64
MAP
BGA
64
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
B8 49 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX FTM0_CH3 CMP1_OUT
A8 50 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2
I2S0_RXD0 CMP0_OUT
A7 51 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_SOUT PDB0_EXTRG I2S0_RX_
BCLK
I2S0_MCLK
B6 52 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_
OUT
I2S0_RX_FS
A6 53 PTC8 CMP0_IN2 CMP0_IN2 PTC8 I2S0_MCLK
B5 54 PTC9 CMP0_IN3 CMP0_IN3 PTC9 I2S0_RX_
BCLK
B4 55 PTC10 DISABLED PTC10 I2S0_RX_FS
A5 56 PTC11/
LLWU_P11
DISABLED PTC11/
LLWU_P11
C3 57 PTD0/
LLWU_P12
DISABLED PTD0/
LLWU_P12
SPI0_PCS0 UART2_RTS_
b
A4 58 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_
b
C2 59 PTD2/
LLWU_P13
DISABLED PTD2/
LLWU_P13
SPI0_SOUT UART2_RX
B3 60 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX
A3 61 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI0_PCS1 UART0_RTS_
b
FTM0_CH4 EWM_IN
C1 62 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_
b/
UART0_COL_
b
FTM0_CH5 EWM_OUT_b
B2 63 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH6 FTM0_FLT0
A2 64 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1
8.2 K20 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
Pinout
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
58 Freescale Semiconductor, Inc.