Information

Table 42. Slave mode DSPI timing (full voltage range) (continued)

Num Description Min. Max. Unit

DS9 DSPI_SCK input cycle time 8 x t

BUS

— ns

DS10 DSPI_SCK input high/low time (t

SCK

/2) - 4 (t

SCK/2)

+ 4 ns

DS11 DSPI_SCK to DSPI_SOUT valid — 20 ns

DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns

DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns

DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns

DS15 DSPI_SS active to DSPI_SOUT driven — 19 ns

DS16 DSPI_SS inactive to DSPI_SOUT not driven — 19 ns

First data Last data

First data Data Last data

Data

DS15

DS10 DS9

DS16

DS11

DS12

DS14

DS13

DSPI_SS

DSPI_SCK

(CPOL=0)

DSPI_SOUT

DSPI_SIN

Figure 24. DSPI classic SPI timing — slave mode

6.8.7 I

C switching specifications

See General switching specifications.

6.8.8 UART switching specifications

See General switching specifications.

6.8.9 I2S/SAI Switching Specifications

This section provides the AC timing for the I2S/SAI module in master mode (clocks are

driven) and slave mode (clocks are input). All timing is given for noninverted serial clock

polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]

Peripheral operating requirements and behaviors

K20 Sub-Family Data Sheet, Rev. 3, 11/2012.

58 Freescale Semiconductor, Inc.