Information
121
MAP
BGA
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
G6 24 VREFL VREFL VREFL
F6 25 VSSA VSSA VSSA
L3 26 VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
K5 27 DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
L7 — RTC_
WAKEUP_B
RTC_
WAKEUP_B
RTC_
WAKEUP_B
L4 28 XTAL32 XTAL32 XTAL32
L5 29 EXTAL32 EXTAL32 EXTAL32
K6 30 VBAT VBAT VBAT
H5 31 PTE24 ADC0_SE17 ADC0_SE17 PTE24 UART4_TX EWM_OUT_b
J5 32 PTE25 ADC0_SE18 ADC0_SE18 PTE25 UART4_RX EWM_IN
H6 33 PTE26 DISABLED PTE26 UART4_CTS_
b
RTC_CLKOUT USB_CLKIN
J6 34 PTA0 JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CTS_
b/
UART0_COL_
b
FTM0_CH5 JTAG_TCLK/
SWD_CLK
EZP_CLK
H8 35 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
J7 36 PTA2 JTAG_TDO/
TRACE_SWO/
EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SWO
EZP_DO
H9 37 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RTS_
b
FTM0_CH0 JTAG_TMS/
SWD_DIO
J8 38 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
K7 39 PTA5 DISABLED PTA5 USB_CLKIN FTM0_CH2 CMP2_OUT I2S0_TX_
BCLK
JTAG_TRST_
b
E5 40 VDD VDD VDD
G3 41 VSS VSS VSS
K8 42 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD0 FTM1_QD_
PHA
L8 43 PTA13/
LLWU_P4
CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_
PHB
K9 44 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_RX_
BCLK
I2S0_TXD1
L9 45 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD0
J10 46 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_
b/
UART0_COL_
b
I2S0_RX_FS I2S0_RXD1
Pinout
K20 Sub-Family Data Sheet, Rev. 3, 11/2012.
66 Freescale Semiconductor, Inc.
