Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 32-Bit 72 MHz I/O number 66

K20 Sub-Family Reference Manual

Supports: MK20DX128VLL7, MK20DX256VLL7, MK20DX64VMC7,

MK20DX128VMC7, MK20DX256VMC7

Document Number: K20P100M72SF1RM

Rev. 1.1, Dec 2012

Preliminary

General Business Information

Summary of content (1449 pages)

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K20 Sub-Family Reference Manual Supports: MK20DX128VLL7, MK20DX256VLL7, MK20DX64VMC7, MK20DX128VMC7, MK20DX256VMC7 Document Number: K20P100M72SF1RM Rev. 1.
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K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 2 Preliminary General Business Information Freescale Semiconductor, Inc.
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Contents Section number Title Page Chapter 1 About This Document 1.1 1.2 Overview.......................................................................................................................................................................51 1.1.1 Purpose.........................................................................................................................................................51 1.1.2 Audience......................................................................
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Section number 3.2 3.3 3.4 3.5 Title Page Core modules................................................................................................................................................................61 3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................61 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................63 3.
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Section number 3.6 Title Page 3.5.5 System Register File Configuration.............................................................................................................95 3.5.6 VBAT Register File Configuration..............................................................................................................96 3.5.7 EzPort Configuration...................................................................................................................................96 3.5.
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Section number 3.7 3.8 3.9 3.10 Title Page Analog...........................................................................................................................................................................101 3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................101 3.7.2 CMP Configuration................................................................................................................
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Section number Title Page 4.4 SRAM memory map.....................................................................................................................................................152 4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................153 4.6 4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................153 4.5.
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Section number Title Page Chapter 6 Reset and Boot 6.1 Introduction...................................................................................................................................................................177 6.2 Reset..............................................................................................................................................................................178 6.3 6.2.1 Power-on reset (POR)....................................................
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Section number 8.3.3 Title Page Security Interactions with Debug.................................................................................................................198 Chapter 9 Debug 9.1 Introduction...................................................................................................................................................................201 9.1.1 9.2 References.........................................................................................................
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Section number 10.3 10.4 Title Page 10.2.3 Clock gating.................................................................................................................................................216 10.2.4 Signal multiplexing constraints....................................................................................................................216 Pinout.......................................................................................................................................
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Section number 12.3 Title Page 12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................258 12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................260 12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................263 12.2.
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Section number 13.2.5 Title Page Mode Register (RCM_MR).........................................................................................................................293 Chapter 14 System Mode Controller 14.1 Introduction...................................................................................................................................................................295 14.2 Modes of operation....................................................................................
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Section number 15.5.3 Title Page Regulator Status And Control register (PMC_REGSC)..............................................................................320 Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.1 Introduction...................................................................................................................................................................323 16.1.1 Features.....................................................................................................
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Section number 17.2 Title Page Memory map/register descriptions...............................................................................................................................345 17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................346 17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................346 17.2.3 Control Register (MCM_CR).......................
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Section number Title Page Chapter 20 Direct Memory Access Multiplexer (DMAMUX) 20.1 Introduction...................................................................................................................................................................381 20.1.1 Overview......................................................................................................................................................381 20.1.2 Features..........................................................
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Section number Title Page 21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................418 21.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................419 21.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................420 21.3.
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Section number 21.3.31 Title Page TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO)............................................................................................................445 21.4 21.5 Functional description...................................................................................................................................................446 21.4.1 eDMA basic data flow..................................................
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Section number Title Page 22.4.2 The EWM_in Signal....................................................................................................................................477 22.4.3 EWM Counter..............................................................................................................................................478 22.4.4 EWM Compare Registers............................................................................................................................
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Section number 23.8 23.9 Title Page 23.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................496 23.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................496 23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................496 23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).....
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Section number 24.4 24.5 Title Page Functional description...................................................................................................................................................520 24.4.1 MCG mode state diagram............................................................................................................................520 24.4.2 Low Power Bit Usage.................................................................................................................
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Section number Title Page 25.11 Interrupts.......................................................................................................................................................................551 Chapter 26 RTC Oscillator 26.1 26.2 Introduction...................................................................................................................................................................553 26.1.1 Features and Modes....................................................
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Section number 27.5 27.6 Title Page 27.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)..........................................................................573 27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL)..........................................................................574 27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)..........................................................................574 27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL)............
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Section number Title Page 28.4.2 FlexNVM Description..................................................................................................................................604 28.4.3 Interrupts......................................................................................................................................................607 28.4.4 Flash Operation in Low-Power Modes........................................................................................................
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Section number 29.5 Title Page 29.4.6 Data transfer signals.....................................................................................................................................656 29.4.7 Signal transitions..........................................................................................................................................656 29.4.8 Data-byte alignment and physical connections.........................................................................................
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Section number Title Page Chapter 31 Cyclic Redundancy Check (CRC) 31.1 31.2 31.3 Introduction...................................................................................................................................................................701 31.1.1 Features........................................................................................................................................................701 31.1.2 Block diagram...................................................
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Section number 32.4 Title Page 32.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................722 32.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................723 32.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................724 32.3.
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Section number 32.5 Page 32.4.5 Conversion control.......................................................................................................................................742 32.4.6 Automatic compare function........................................................................................................................749 32.4.7 Calibration function...................................................................................................................................
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Section number 33.8 33.9 Title Page CMP functional description..........................................................................................................................................776 33.8.1 CMP functional modes.................................................................................................................................776 33.8.2 Power modes...........................................................................................................................
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Section number 34.5.4 Title Page Low-Power mode operation.........................................................................................................................801 Chapter 35 Voltage Reference (VREFV1) 35.1 35.2 35.3 35.4 Introduction...................................................................................................................................................................803 35.1.1 Overview.....................................................................
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Section number 36.4 36.5 Title Page 36.3.4 Interrupt Delay Register (PDBx_IDLY)......................................................................................................820 36.3.5 Channel n Control Register 1 (PDBx_CHnC1)...........................................................................................821 36.3.6 Channel n Status Register (PDBx_CHnS)...................................................................................................822 36.3.
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Section number 37.4 Title Page 37.3.2 Register descriptions....................................................................................................................................839 37.3.3 Status And Control (FTMx_SC)..................................................................................................................844 37.3.4 Counter (FTMx_CNT).................................................................................................................................
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Section number Title Page 37.4.3 Counter.........................................................................................................................................................888 37.4.4 Input Capture mode......................................................................................................................................893 37.4.5 Output Compare mode......................................................................................................................
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Section number Title Page 37.6.2 Channel (n) Interrupt....................................................................................................................................963 37.6.3 Fault Interrupt..............................................................................................................................................963 Chapter 38 Periodic Interrupt Timer (PIT) 38.1 Introduction.......................................................................................
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Section number 39.4 Title Page 39.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................979 39.3.3 Low Power Timer Compare Register (LPTMRx_CMR).............................................................................980 39.3.4 Low Power Timer Counter Register (LPTMRx_CNR)...............................................................................981 Functional description............................................
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Section number 40.7 40.8 Title Page 40.6.8 CMT Modulator Data Register Mark Low (CMT_CMD2).........................................................................997 40.6.9 CMT Modulator Data Register Space High (CMT_CMD3).......................................................................997 40.6.10 CMT Modulator Data Register Space Low (CMT_CMD4)........................................................................998 40.6.11 CMT Primary Prescaler Register (CMT_PPS)......................
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Section number 41.3 Title Page Functional description...................................................................................................................................................1023 41.3.1 Power, clocking, and reset...........................................................................................................................1023 41.3.2 Time counter.........................................................................................................................
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Section number Title Page 42.5.5 OTG Interrupt Status register (USBx_OTGISTAT)....................................................................................1043 42.5.6 OTG Interrupt Control Register (USBx_OTGICR).....................................................................................1044 42.5.7 OTG Status register (USBx_OTGSTAT)....................................................................................................1045 42.5.8 OTG Control register (USBx_OTGCTL).......
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Section number 42.9 Title Page Hardware Interface........................................................................................................................................................1069 42.9.1 ......................................................................................................................................................................1069 42.10 System Level Issues and Configuration................................................................................
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Section number 43.7 Title Page Application information................................................................................................................................................1096 43.7.1 External pullups...........................................................................................................................................1096 43.7.2 Dead or weak battery.............................................................................................................
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Section number 45.4 45.5 Title Page 45.3.9 Error and Status 1 register (CANx_ESR1)..................................................................................................1125 45.3.10 Interrupt Masks 1 register (CANx_IMASK1).............................................................................................1129 45.3.11 Interrupt Flags 1 register (CANx_IFLAG1)................................................................................................1130 45.3.
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Section number Title Page Chapter 46 Serial Peripheral Interface (SPI) 46.1 46.2 46.3 46.4 Introduction...................................................................................................................................................................1181 46.1.1 Block Diagram.............................................................................................................................................1181 46.1.2 Features..................................................
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Section number 46.5 Title Page 46.4.2 Serial Peripheral Interface (SPI) configuration............................................................................................1210 46.4.3 Module baud rate and clock delay generation.............................................................................................1214 46.4.4 Transfer formats...........................................................................................................................................1216 46.4.
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Section number 47.4 47.5 Title Page 47.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................1244 47.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................1244 47.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................1246 47.3.
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Section number Title Page 48.3.6 UART Status Register 2 (UARTx_S2)........................................................................................................1288 48.3.7 UART Control Register 3 (UARTx_C3).....................................................................................................1290 48.3.8 UART Data Register (UARTx_D)...............................................................................................................1291 48.3.
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Section number 48.4 Title Page 48.3.35 UART CEA709.1-B Beta1 Timer (UARTx_B1T)......................................................................................1312 48.3.36 UART CEA709.1-B Secondary Delay Timer High (UARTx_SDTH)........................................................1313 48.3.37 UART CEA709.1-B Secondary Delay Timer Low (UARTx_SDTL).........................................................1313 48.3.38 UART CEA709.1-B Preamble (UARTx_PRE)........................................
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Section number 48.8 Title Page Application information................................................................................................................................................1359 48.8.1 Transmit/receive data buffer operation........................................................................................................1359 48.8.2 ISO-7816 initialization sequence..............................................................................................................
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Section number 49.4 Title Page 49.3.11 SAI Receive Configuration 1 Register (I2Sx_RCR1)..................................................................................1386 49.3.12 SAI Receive Configuration 2 Register (I2Sx_RCR2)..................................................................................1386 49.3.13 SAI Receive Configuration 3 Register (I2Sx_RCR3)..................................................................................1388 49.3.
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Section number 50.3 Title Page 50.2.5 Port Data Input Register (GPIOx_PDIR).....................................................................................................1409 50.2.6 Port Data Direction Register (GPIOx_PDDR).............................................................................................1409 Functional description...................................................................................................................................................1409 50.
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Section number 51.7 51.8 Page Functional description...................................................................................................................................................1427 51.7.1 Capacitance measurement............................................................................................................................1427 51.7.2 TSI measurement result..................................................................................................................
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Section number 52.5 Title Page 52.4.3 TAP controller state machine.......................................................................................................................1443 52.4.4 JTAGC block instructions............................................................................................................................1445 52.4.5 Boundary scan.....................................................................................................................................
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Chapter 1 About This Document 1.1 Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale K20 microcontroller. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using the K20 microcontroller in a system. 1.2 Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems: This suffix Identifies a b Binary number.
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Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers. code Fixed-width type indicates text that must be typed exactly as shown.
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Chapter 2 Introduction 2.1 Overview This chapter provides high-level descriptions of the modules available on the devices covered by this document. 2.2 Module Functional Categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Table 2-1. Module functional categories Module category Description ARM Cortex-M4 core • 32-bit MCU core from ARM’s Cortex-M class adding DSP instructions, 1.
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Module Functional Categories Table 2-1.
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Chapter 2 Introduction Table 2-2. Core modules (continued) Module Description NVIC The ARMv7-M exception model and nested-vectored interrupt controller (NVIC) implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (NMI), and priority levels. The NVIC replaces shadow registers with equivalent system and simplified programmability. The NVIC contains the address of the function to execute for a particular handler.
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Module Functional Categories Table 2-3. System modules (continued) Module Description Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control descriptors for data movement via dual-address transfers for 8-, 16-, 32- and 128bit data values. External watchdog monitor (EWM) The EWM is a redundant mechanism to the software watchdog module that monitors both internal and external system operation for fail conditions.
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Chapter 2 Introduction 2.2.4 Clocks The following clock modules are available on this device. Table 2-5.
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Module Functional Categories Table 2-7. Analog modules (continued) Module Description Voltage reference (VREF) Supplies an accurate voltage output that is trimmable in 0.5 mV steps. The VREF can be used in medical applications, such as glucose meters, to provide a reference voltage to biosensors or as a reference to analog peripherals, such as the ADC, DAC, or CMP. 2.2.7 Timer modules The following timer modules are available on this device: Table 2-8.
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Chapter 2 Introduction Table 2-8. Timer modules (continued) Module Description Low-power timer (LPTimer) • Selectable clock for prescaler/glitch filter of 1 kHz (internal LPO), 32.
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Orderable part numbers 2.2.9 Human-machine interfaces The following human-machine interfaces (HMI) are available on this device: Table 2-10. HMI modules Module Description General purpose input/output (GPIO) All general purpose input or output (GPIO) pins are capable of interrupt and DMA request generation. All GPIO pins have 5 V tolerance. Capacitive touch sense input (TSI) Contains up to 16 channel inputs for capacitive touch sensing applications.
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Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: • module block diagrams showing immediate connections within the device, • specific module-to-module interactions not necessarily discussed in the individual module chapters, and • links for more information. 3.2 Core modules 3.2.1 ARM Cortex-M4 Core Configuration This section summarizes how the module has been configured in the chip.
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Core modules Debug Interrupts PPB ARM Cortex-M4 Core Crossbar switch PPB Modules SRAM Upper SRAM Lower Figure 3-1. Core configuration Table 3-1.
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Chapter 3 Chip Configuration Bus name Description System bus The system bus is connected to a separate master port on the crossbar. In addition, the system bus is tightly coupled to the upper half system RAM (SRAM_U). Private peripheral (PPB) bus The PPB provides access to these modules: • ARM modules such as the NVIC, ITM, DWT, FBP, and ROM table • Freescale Miscellaneous Control Module (MCM) 3.2.1.2 System Tick Timer The System Tick Timer's clock source is always the core clock, FCLK.
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Core modules ARM Cortex-M4 core Interrupts Module Nested Vectored Interrupt Controller (NVIC) PPB Module Module Figure 3-2. NVIC configuration Table 3-2.
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Chapter 3 Chip Configuration • Vector number — the value stored on the stack when an interrupt is serviced. • IRQ number — non-core interrupt source count, which is the vector number minus 16. The IRQ number is used within ARM's NVIC documentation. Table 3-4.
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Core modules Table 3-4.
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Chapter 3 Chip Configuration Table 3-4.
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Core modules Table 3-4.
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Chapter 3 Chip Configuration Table 3-5. LPTMR interrupt vector assignment Address IRQ1 Vector NVIC NVIC non-IPR IPR register register number number 2 0x0000_0194 101 85 2 Source module Source description 3 21 Low Power Timer — 1. Indicates the NVIC's interrupt source number. 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ.
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Core modules Clock logic Nested vectored interrupt controller (NVIC) Wake-up requests Asynchronous Wake-up Interrupt Controller (AWIC) Module Module Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration Table 3-6. Reference links to related information Topic Related module Reference System memory map System memory map Clocking Clock distribution Power management Power management Nested Vectored Interrupt Controller (NVIC) Wake-up requests NVIC AWIC wake-up sources 3.2.3.
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Chapter 3 Chip Configuration 3.2.4 JTAG Controller Configuration cJTAG JTAG controller Signal multiplexing This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Figure 3-4. JTAGC Controller configuration Table 3-8. Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control Signal multiplexing 3.3 System modules 3.
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System modules Peripheral bridge Register access System integration module (SIM) Figure 3-5. SIM configuration Table 3-9. Reference links to related information Topic Related module Reference Full description SIM SIM System memory map System memory map Clocking Clock distribution Power management Power management 3.3.2 System Mode Controller (SMC) Configuration This section summarizes how the module has been configured in the chip.
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Chapter 3 Chip Configuration Table 3-10. Reference links to related information (continued) Topic Related module Reference Power management controller (PMC) PMC Low-Leakage Wakeup Unit (LLWU) LLWU Reset Control Module (RCM) Reset 3.3.3 PMC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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System modules 3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 Register access Power Management Controller (PMC) Wake-up requests Low-Leakage Wake-up Unit (LLWU) Module Module Figure 3-8. Low-Leakage Wake-up Unit configuration Table 3-12.
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Chapter 3 Chip Configuration Table 3-13.
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System modules 3.3.6 Crossbar Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Table 3-15.
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Chapter 3 Chip Configuration 3.3.6.2 Crossbar Switch Slave Assignments The slaves connected to the crossbar switch are assigned as follows: Slave module Slave port number Flash memory controller 0 SRAM backdoor 1 Peripheral bridge 01 2 Peripheral bridge 1/GPIO1 3 FlexBus 4 1. See System memory map for access restrictions. 3.3.6.3 PRS register reset values The AXBS_PRSn registers reset to 0000_3210h. 3.3.
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System modules 3.3.7.2 Memory maps The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map and AIPS1 Memory Map for the memory slot assignment for each module. 3.3.7.3 MPRA register Each of the two peripheral bridges supports up to 8 crossbar switch masters, each assigned to a MPROTx field in the MPRA register. However, fewer are supported on this device. See Crossbar switch for details of the master port assignments for this device. 3.3.7.
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Chapter 3 Chip Configuration Peripheral bridge 0 Register access DMA controller Requests Channel request DMA Request Multiplexer Module Module Module Figure 3-11. DMA request multiplexer configuration Table 3-17.
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System modules Table 3-18.
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Chapter 3 Chip Configuration Table 3-18.
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System modules Peripheral bridge 0 Transfers DMA Controller Requests DMA Multiplexer Crossbar switch Register access Figure 3-12. DMA Controller configuration Table 3-19.
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Chapter 3 Chip Configuration Peripheral bridge 0 External Watchdog Monitor (EWM) Module signals Signal multiplexing Register access Figure 3-13. External Watchdog Monitor configuration Table 3-20. Reference links to related information Topic Related module Reference Full description External Watchdog Monitor (EWM) EWM System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port Control Module Signal multiplexing 3.3.10.
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System modules 3.3.10.3 EWM_OUT pin state in low power modes During Wait, Stop and Power Down modes the EWM_OUT pin enters a high-impedance state. A user has the option to control the logic state of the pin using an external pull device or by configuring the internal pull device. When the CPU enters a Run mode from Wait or Stop recovery, the pin resumes its previous state before entering Wait or Stop mode. When the CPU enters Run mode from Power Down, the pin returns to its reset state. 3.3.
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Chapter 3 Chip Configuration Table 3-24. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Alt Clock Bus Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock 3.3.11.2 WDOG low-power modes This table shows the WDOG low-power modes and the corresponding chip low-power modes. Table 3-25. WDOG low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS Power Down LLS, VLLSx 3.4 Clock modules 3.4.
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Clock modules Peripheral bridge System integration module (SIM) RTC System oscillator oscillator Register access Multipurpose Clock Generator (MCG) Figure 3-15. MCG configuration Table 3-26. Reference links to related information Topic Related module Reference Full description MCG MCG System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.4.
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Chapter 3 Chip Configuration Table 3-27. Reference links to related information (continued) Topic Related module Reference Power management Power management Signal multiplexing Port control Signal multiplexing Full description MCG MCG 3.4.2.1 OSC modes of operation with MCG The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details. 3.4.
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Memories and memory interfaces Peripheral bus controller 0 Flash memory controller Register access Transfers Flash memory Figure 3-18. Flash memory configuration Table 3-29. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory System memory map System memory map Clocking Clock Distribution Transfers Flash memory controller Flash memory controller Register access Peripheral bridge Peripheral bridge 3.5.1.
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Chapter 3 Chip Configuration Device Program flash (KB) Block 0 (PFlash) address range FlexNVM (KB) Block 1 (FlexNVM) address range FlexRAM (KB) FlexRAM address range MK20DX128VL L7 128 0x0000_0000 – 0x0003_FFFF 32 0x1000_0000 – 0x1000_7FFF 2 0x1400_0000 – 0x1400_07FF MK20DX256VL L7 256 0x0000_0000 – 0x0003_FFFF 32 0x1000_0000 – 0x1000_7FFF 2 0x1400_0000 – 0x1400_07FF MK20DX64VM C7 64 0x0000_0000 – 0x0003_FFFF 32 0x1000_0000 – 0x1000_7FFF 2 0x1400_0000 – 0x1400_07FF MK20DX128VM 1
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Memories and memory interfaces 3.5.1.5 Flash Modes The flash memory operates in NVM normal and NVM special modes. The flash memory enters NVM special mode when the EzPort is enabled (EZP_CS asserted during reset). Otherwise, flash memory operates in NVM normal mode. 3.5.1.6 Erase All Flash Contents In addition to software, the entire flash memory may be erased external to the flash memory in two ways: 1. Via the EzPort by issuing a bulk erase (BE) command. See the EzPort chapter for more details. 2.
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Chapter 3 Chip Configuration Peripheral bus controller 0 Transfers Flash memory controller Transfers Flash memory Crossbar switch Register access Figure 3-20. Flash memory controller configuration Table 3-30.
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Memories and memory interfaces 3.5.3.1 SRAM sizes This device contains SRAM tightly coupled to the ARM Cortex-M4 core. The amount of SRAM for the devices covered in this document is shown in the following table. Device SRAM (KB) MK20DX128VLL7 32 MK20DX256VLL7 64 MK20DX64VMC7 16 MK20DX128VMC7 32 MK20DX256VMC7 64 3.5.3.2 SRAM Arrays The on-chip SRAM is split into two equally-sized logical arrays, SRAM_L and SRAM_U.
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Chapter 3 Chip Configuration SRAM size / 2 SRAM_L SRAM size / 2 0x2000_0000 – SRAM_size/2 SRAM_U 0x1FFF_FFFF 0x2000_0000 0x2000_0000 + SRAM_size/2 - 1 Figure 3-22. SRAM blocks memory map For example, for a device containing 64 KB of SRAM the ranges are: • SRAM_L: 0x1FFF_8000 – 0x1FFF_FFFF • SRAM_U: 0x2000_0000 – 0x2000_7FFF 3.5.3.3 SRAM retention in low power modes The SRAM is retained down to VLLS3 mode. In VLLS2 the 16 KB region of SRAM_U from 0x2000_0000 is powered.
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Memories and memory interfaces SRAM_L Cortex-M4 core Crossbar switch non-core master Backdoor Frontdoor Code bus non-core master SRAM controller System bus non-core master SRAM_U Figure 3-23. SRAM access diagram The following simultaneous accesses can be made to different logical halves of the SRAM: • Core code and core system • Core code and non-core master • Core system and non-core master NOTE Two non-core masters cannot access SRAM simultaneously.
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Cortex-M4 core Transfers SRAM lower SRAM controller SRAM upper Chapter 3 Chip Configuration Crossbar switch Figure 3-24. SRAM controller configuration Table 3-32. Reference links to related information Topic Related module Reference System memory map System memory map Power management Power management Power management controller (PMC) PMC Transfers SRAM SRAM ARM Cortex-M4 core ARM Cortex-M4 core MCM MCM Configuration 3.5.
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Memories and memory interfaces 3.5.5.1 System Register file This device includes a 32-byte register file that is powered in all power modes. Also, it retains contents during low-voltage detect (LVD) events and is only reset during a power-on reset. 3.5.6 VBAT Register File Configuration This section summarizes how the module has been configured in the chip. Peripheral bridge Register access VBAT register file Figure 3-26. VBAT Register file configuration Table 3-34.
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Chapter 3 Chip Configuration 3.5.7 EzPort Configuration Transfers EzPort Module signals Signal multiplexing Crossbar switch This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Figure 3-27. EzPort configuration Table 3-35.
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Memories and memory interfaces 3.5.8 FlexBus Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 Transfers FlexBus Module signals Signal multiplexing Crossbar switch Register access Figure 3-28. FlexBus configuration Table 3-36.
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Chapter 3 Chip Configuration FB_CS4 FB_TSIZ0 Group2 FB_BE_31_24 Reserved FB_CS5 FB_TSIZ1 Group3 FB_BE_23_16 Reserved FB_TBST FB_CS2 Group4 FB_BE_15_8 Reserved FB_TA FB_CS3 Group5 FB_BE_7_0 External Pins Reserved To other modules Group1 FB_TS To other modules FB_CS1 To other modules FB_ALE To other modules CSPMCR Port Control Module To other modules FlexBus Reserved Figure 3-29. FlexBus control signal multiplexing K20 Sub-Family Reference Manual, Rev. 1.
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Security Therefore, use the CSPMCR and port control registers to configure which control signal is available on the external pin. All control signals, except for FB_TA, are assigned to the ALT5 function in the port control module. Since, unlike the other control signals, FB_TA is an input signal, it is assigned to the ALT6 function. 3.5.8.3 FlexBus CSCR0 reset value On this device the CSCR0 resets to 0x003F_FC00. Configure this register as needed before performing any FlexBus access. 3.5.8.
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Chapter 3 Chip Configuration Peripheral bridge Register access CRC Figure 3-30. CRC configuration Table 3-37. Reference links to related information Topic Related module Reference Full description CRC CRC System memory map System memory map Power management Power management 3.7 Analog 3.7.1 16-bit SAR ADC with PGA Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Analog Peripheral bus controller 0 Transfers Other peripherals Module signals 16-bit SAR ADC Signal multiplexing Register access Figure 3-31. 16-bit SAR ADC with PGA configuration Table 3-38. Reference links to related information Topic Related module Reference Full description 16-bit SAR ADC with PGA 16-bit SAR ADC with PGA System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.1.
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Chapter 3 Chip Configuration 3.7.1.3 Connections/Channel Assignment 3.7.1.3.1 ADC0 Connections/Channel Assignment NOTE As indicated by the following sections, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended ADC channels in single-ended mode. 3.7.1.3.1.
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Connections/Channel Assignment ADC Channel (SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 10111 AD23 Reserved 12-bit DAC0 Output/ ADC0_SE23 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff)9 Bandgap (S.E)9 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled 1.
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Chapter 3 Chip Configuration ADC Channel (SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 01100 AD12 Reserved ADC0_SE12 01101 AD13 Reserved ADC0_SE13 01110 AD14 Reserved ADC0_SE14 01111 AD15 Reserved ADC0_SE15 10000 AD16 Reserved Reserved 10001 AD17 Reserved ADC0_SE17 10010 AD18 Reserved ADC0_SE18 10011 AD19 Reserved ADC0_DM08 10100 AD20 Reserved ADC0_DM1 10101 AD21 Reserved 10110 AD22 Reserved 10111 AD23 Reserved 12-bit DAC0 Ou
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Connections/Channel Assignment 3.7.1.4.
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Chapter 3 Chip Configuration 4. Interleaved with ADC0_DP0 5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 6. Interleaved with ADC0_SE8 7. Interleaved with ADC0_SE9 8. Interleaved with ADC0_DM3 9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit.
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Connections/Channel Assignment ADC Channel (SC1n[ADCH]) 11010 Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) AD26 Temperature Sensor (Diff) 11011 AD27 Bandgap (Diff)9 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled 1. 2. 3. 4. 5. 6. 7. 8. 9. Temperature Sensor (S.E) Bandgap (S.
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Chapter 3 Chip Configuration ADC0 ADC0_SE8/ADC1_SE8 AD8 ADC0_SE9/ADC1_SE9 AD9 AD8 ADC1 AD9 Figure 3-33. ADC hardware interleaved channels integration 3.7.1.7 ADC and PGA Reference Options The ADC supports the following references: • VREFH/VREFL - connected as the primary reference option • 1.2 V VREF_OUT - connected as the VALT reference option ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC. Refer to REFSEL description in ADC chapter for more details.
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Connections/Channel Assignment 3.7.1.8 ADC triggers The ADC supports both software and hardware triggers. The primary hardware mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other peripherals. For example: RTC (Alarm, Seconds) signal is connected to the PDB. The PDB trigger can receive the RTC (alarm/seconds) trigger input forcing ADC conversions in run mode (where PDB is enabled). On the other hand, the ADC can conduct conversions in low power modes, not triggered by PDB.
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Chapter 3 Chip Configuration • Each PGA connects to the differential ADC channels • The PGA outputs differential pairs that are connected to ADC differential input • When the PGA is used, differential input from the pins is connected to differential input channel 2 on ADCx ADC0 ADC0_DP1 ADC0_DM1 DAD1 DAD0 PGA0_DP/ADC0_DP0/ADC1_DP3 PGA0_DM/ADC0_DM0/ADC1_DM3 PGA0 DAD2 DAD3 ADC1 DAD3 PGA1_DP/ADC1_DP0/ADC0_DP3 PGA1_DM/ADC1_DM0/ADC0_DM3 PGA1 DAD2 DAD0 ADC1_DP1 ADC1_DM1 DAD1 Figure 3-34.
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Connections/Channel Assignment Peripheral bridge 0 Module signals CMP Other peripherals Signal multiplexing Register access Figure 3-35. CMP configuration Table 3-40. Reference links to related information Topic Related module Reference Full description Comparator (CMP) Comparator System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.2.
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Chapter 3 Chip Configuration • VREF_OUT - Vin1 input • VDD - Vin2 input 3.7.2.3 External window/sample input Individual PDB pulse-out signals control each CMP Sample/Window timing. 3.7.3 12-bit DAC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Connections/Channel Assignment 3.7.3.2 12-bit DAC Output The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. 3.7.3.3 12-bit DAC Reference For this device VREF_OUT and VDDA are selectable as the DAC reference. VREF_OUT is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input. Use DACx_C0[DACRFS] control bit to select between these two options.
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Chapter 3 Chip Configuration 3.7.4.1 VREF Overview This device includes a voltage reference (VREF) to supply an accurate 1.2 V voltage output. The voltage reference can provide a reference voltage to external peripherals or a reference to analog peripherals, such as the ADC, DAC, or CMP. NOTE PMC_REGSC[BGEN] bit must be set if the VREF regulator is required to remain operating in VLPx modes.
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Timers Table 3-44. Reference links to related information (continued) Topic Related module Reference Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.1.1 PDB Instantiation 3.8.1.1.1 3.8.1.1.2 PDB Output Triggers Table 3-45. PDB output triggers Number of PDB channels for ADC trigger 2 Number of pre-triggers per PDB channel 2 Number of DAC triggers 1 Number of PulseOut 3 PDB Input Trigger Connections Table 3-46.
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Chapter 3 Chip Configuration 3.8.1.2 PDB Module Interconnections PDB trigger outputs Connection Channel 0 triggers ADC0 trigger Channel 1 triggers ADC1 trigger and synchronous input 1 of FTM0 DAC triggers DAC0 trigger Pulse-out Pulse-out connected to each CMP module's sample/window input to control sample operation 3.8.1.
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Timers 3.8.1.5 DAC External Trigger Input Connections In this MCU, the following DAC external trigger inputs are implemented. • DAC external trigger input 0: ADC0SC1A_COCO • DAC external trigger input 1: ADC1SC1A_COCO NOTE Application code can set the PDBx_DACINTCn[EXT] bit to allow DAC external trigger input when the corresponding ADC Conversion complete flag, ADCx_SC1n[COCO], is set. 3.8.1.6 Pulse-Out Connection Individual PDB Pulse-Out signals are connected to each CMP block and used for sample window.
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Chapter 3 Chip Configuration Peripheral bus controller 0 Transfers Module signals FlexTimer Other peripherals Signal multiplexing Register access Figure 3-40. FlexTimer configuration Table 3-48. Reference links to related information Topic Related module Reference Full description FlexTimer FlexTimer System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.2.
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Timers 3.8.2.2 External Clock Options By default each FTM is clocked by the internal bus clock (the FTM refers to it as system clock). Each module contains a register setting that allows the module to be clocked from an external clock instead. There are two external FTM_CLKINx pins that can be selected by any FTM module via the SOPT4 register in the SIM module. 3.8.2.3 Fixed frequency clock The fixed frequency clock for each FTM is MCGFFCLK. 3.8.2.
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Chapter 3 Chip Configuration • FTM0 hardware trigger 0 = CMP0 Output or FTM1 Match (when enabled in the FTM1 External Trigger (EXTTRIG) register) • FTM0 hardware trigger 1 = PDB channel 1 Trigger Output or FTM2 Match (when enabled in the FTM2 External Trigger (EXTTRIG) register) • FTM0 hardware trigger 2 = FTM0_FLT0 pin • FTM1 hardware trigger 0 = CMP0 Output • FTM1 hardware trigger 1 = CMP1 Output • FTM1 hardware trigger 2 = FTM1_FLT0 pin • FTM2 hardware trigger 0 = CMP0 Output • FTM2 hardware trigger 1 =
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Timers FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: FTM1 CONF Register GTBEOUT = 0 GTBEEN = 1 FTM0 CONF Register GTBEOUT = 1 GTBEEN = 1 FTM Counter gtb_in gtb_in FTM Counter FTM2 gtb_out CONF Register GTBEOUT = 0 GTBEEN = 1 FTM Counter gtb_in Figure 3-41. FTM Global Time Base Configuration 3.8.2.
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Chapter 3 Chip Configuration Table 3-50. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.3.1 PIT/DMA Periodic Trigger Assignments The PIT generates periodic trigger events to the DMA Mux as shown in the table below. Table 3-51.
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Timers Peripheral bridge Module signals Low-power timer Signal multiplexing Register access Figure 3-43. LPT configuration Table 3-52. Reference links to related information Topic Related module Reference Full description Low-power timer Low-power timer System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.8.4.
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Chapter 3 Chip Configuration 3.8.4.2 LPTMR pulse counter input options The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input 00 0 CMP0 output 01 1 LPTMR_ALT1 pin 10 2 LPTMR_ALT2 pin 11 3 Reserved 3.8.5 CMT Configuration This section summarizes how the module has been configured in the chip.
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Timers 3.8.5.2 IRO Drive Strength The IRO pad requires higher current drive than can be obtained from a single pad. For this device, the pin associated with the CMT_IRO signal is doubled bonded to two pads. The SOPT2[PTD7PAD] field in SIM module can be used to configure the pin associated with the CMT_IRO signal as a higher current output port pin. 3.8.6 RTC configuration This section summarizes how the module has been configured in the chip.
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Chapter 3 Chip Configuration RTC_CR[CLKO] RTC 32kHz clock RTC_CLKOUT RTC 1Hz clock SIM_SOPT2[RTCCLKOUTSEL] Figure 3-46. RTC_CLKOUT generation 3.9 Communication interfaces 3.9.1 Universal Serial Bus (USB) FS Subsystem The USB FS subsystem includes these components: • Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS) device or FS/LS host. The module complies with the USB 2.0 specification.
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Communication interfaces 3.9.1.1 USB Wakeup When the USB detects that there is no activity on the USB bus for more than 3 ms, the INT_STAT[SLEEP] bit is set. This bit can cause an interrupt and software decides the appropriate action. Waking from a low power mode (except in LLS/VLLS mode where USB is not powered) occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting the USBTRC0[USBRESMEN] bit enables this function. 3.9.1.
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Chapter 3 Chip Configuration 3.9.1.2.2 Li-Ion battery power supply The chip can also be powered by a single Li-ion battery. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU. When connected to a USB host, the input source of this regulator is switched to the USB bus supply from the Li-ion battery. To charge the battery, the MCU can configure the battery charger according to the charger detection information.
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Communication interfaces VDD To PMC and Pads VOUT33 Cstab Chip TYPE A VBUS VREGIN D+ USB0_DP D- USB0_DM USB Regulator USB XCVR USB Controller Figure 3-50. USB regulator bus supply 3.9.1.3 USB power management The regulator should be put into STANDBY mode whenever the chip is in Stop mode. 3.9.1.4 USB controller configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Chapter 3 Chip Configuration Table 3-55. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing NOTE When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating. 3.9.1.5 USB DCD Configuration This section summarizes how the module has been configured in the chip.
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USB Voltage Regulator Module signals Signal multiplexing USB OTG Communication interfaces Figure 3-53. USB Voltage Regulator configuration Table 3-57.
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Chapter 3 Chip Configuration Table 3-58. Reference links to related information (continued) Topic Related module Power management Signal Multiplexing Reference Power management Port control Signal Multiplexing 3.9.2.1 Reset value of MDIS bit The CAN_MCR[MDIS] bit is set after reset. Therefore, FlexCAN module is disabled following a reset. 3.9.2.2 Number of message buffers Each FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes. 3.9.2.3 FlexCAN Clocking 3.9.2.3.
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Communication interfaces Request Sources Message buffer Message buffers 0-15 Bus off Bus off Error • • • • • • • • Bit1 error Bit0 error Acknowledge error Cyclic redundancy check (CRC) error Form error Stuffing error Transmit error warning Receive error warning Transmit Warning Transmit Warning Receive Warning Receive Warning Wake-up Wake-up 3.9.2.5 FlexCAN Operation in Low Power Modes The FlexCAN module is operational in VLPR and VLPW modes.
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Chapter 3 Chip Configuration Peripheral bridge SPI Module signals Signal multiplexing Register access Figure 3-55. SPI configuration Table 3-59. Reference links to related information Topic Related module Reference Full description SPI SPI System memory map System memory map Clocking Clock Distribution Signal Multiplexing Port control Signal Multiplexing 3.9.3.1 SPI Modules Configuration This device contains two SPI modules. 3.9.3.
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Communication interfaces 3.9.3.4 TX FIFO size Table 3-60. SPI transmit FIFO size SPI Module Transmit FIFO size SPI0 4 SPI1 4 3.9.3.5 RX FIFO Size SPI supports up to 16-bit frame size during reception. Table 3-61. SPI receive FIFO size SPI Module Receive FIFO size SPI0 4 SPI1 4 3.9.3.6 Number of PCS signals The following table shows the number of peripheral chip select signals available per SPI module. Table 3-62.
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Chapter 3 Chip Configuration There is one way to wake from stop mode via the SPI, which is explained in the following section. 3.9.3.7.1 Using GPIO Interrupt to Wake from stop mode Here are the steps to use a GPIO to create a wakeup upon reception of SPI data in slave mode: 1. Point the GPIO interrupt vector to the desired interrupt handler. 2. Enable the GPIO input to generate an interrupt on either the rising or falling edge (depending on the polarity of the chip select signal). 3.
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Communication interfaces 3.9.4 I2C Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge I2 C Module signals Signal multiplexing Register access Figure 3-56. I2C configuration Table 3-64.
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Chapter 3 Chip Configuration Peripheral bridge Module signals UART Signal multiplexing Register access Figure 3-57. UART configuration Table 3-65. Reference links to related information Topic Related module Reference Full description UART UART System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.5.1 UART configuration information This device contains five UART modules.
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Communication interfaces 3.9.5.2 UART wakeup The UART can be configured to generate an interrupt/wakeup on the first active edge that it receives. 3.9.5.3 UART interrupts The UART has multiple sources of interrupt requests. However, some of these sources are OR'd together to generate a single interrupt request.
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Chapter 3 Chip Configuration Source UART 0 UART 1 UART 2 UART 3 UART 4 Character wait timer (ISO7816) x — — — — Block wait timer (ISO7816) x — — — — Guard time x violation (ISO7816) — — — — The LON status interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 UART 3 UART 4 Wbase expire after x beta1 time slots (LON) — — — — Package received (LON) x — — — — Package transmitted (LON) x — — — — Package cycle x time expired (LON) — — —
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Communication interfaces Peripheral bridge I2 S Module signals Signal multiplexing Register access Figure 3-58. I2S configuration Table 3-66. Reference links to related information Topic Related module Reference Full description I2S I2S System memory map System memory map Clocking Clock Distribution Power management Power management Signal multiplexing Port control Signal Multiplexing 3.9.6.1 Instantiation information This device contains one I2S module.
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Chapter 3 Chip Configuration 3.9.6.2.2 Bit Clock The I2S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can be generated internally from the audio master clock or supplied externally. The module also supports the option for synchronous operation between the receiver and transmitterproduct. 3.9.6.2.3 Bus Clock The bus clock is used by the control registers and to generate synchronous interrupts and DMA requests. 3.9.6.2.
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Human-machine interfaces 3.9.6.2.5 Clock gating and I2S/SAI initialization The clock to the I2S/SAI module can be gated using a bit in the SIM. To minimize power consumption, these bits are cleared after any reset, which disables the clock to the corresponding module. The clock enable bit should be set by software at the beginning of the module initialization routine to enable the module clock before initialization of any of the I2S/SAI registers. 3.9.6.3 I2S/SAI operation in low power modes 3.9.6.3.
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Chapter 3 Chip Configuration Peripheral bridge Transfers Module signals GPIO controller Signal multiplexing Crossbar switch Register access Figure 3-59. GPIO configuration Table 3-68. Reference links to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking Clock Distribution Power management Power management Transfers Crossbar switch Clock Distribution Signal Multiplexing Port control Signal Multiplexing 3.10.1.
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Human-machine interfaces Peripheral bridge Touch sense input module Module signals Signal multiplexing Register access Figure 3-60. TSI configuration Table 3-69. Reference links to related information Topic Related module Reference Full description TSI TSI System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.10.2.1 Number of inputs This device includes one TSI module containing 16 inputs.
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Chapter 3 Chip Configuration Table 3-70.
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Human-machine interfaces K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 148 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in one 32-bit contiguous memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. Table 4-1.
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System memory map Table 4-1.
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Chapter 4 Memory Map Bit-band region 31 Alias bit-band region 31 0 32 MByte 1 MByte 0 Figure 4-1. Alias bit-band mapping NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region. 4.3 Flash Memory Map The various flash memories and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map.
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SRAM memory map Flash memory base address Registers Program flash base address Flash configuration field Program flash FlexNVM base address FlexNVM FlexRAM base address FlexRAM Figure 4-2. Flash memory map 4.3.1 Alternate Non-Volatile IRC User Trim Description The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location.
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Chapter 4 Memory Map 4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps The peripheral memory map is accessible via two slave ports on the crossbar switch in the 0x4000_0000–0x400F_FFFF region. The device implements two peripheral bridges (AIPS-Lite 0 and 1): • AIPS-Lite0 covers 512 KB • AIPS-Lite1 covers 508 KB with 4 KB assigned to the general purpose input/output module (GPIO) AIPS-Lite0 is connected to crossbar switch slave port 2, and is accessible at locations 0x4000_0000–0x4007_FFFF.
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Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-2.
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Chapter 4 Memory Map Table 4-2.
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Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-2.
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Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4007_B000 123 — 0x4007_C000 124 Low-leakage wakeup unit (LLWU) 0x4007_D000 125 Power management controller (PMC) 0x4007_E000 126 System Mode controller (SMC) 0x4007_F000 127 Reset Control Module (RCM) 4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map Table 4-3.
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Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps Table 4-3.
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Chapter 4 Memory Map Table 4-3.
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Private Peripheral Bus (PPB) memory map Table 4-3.
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Chapter 4 Memory Map Table 4-4.
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Private Peripheral Bus (PPB) memory map K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 162 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 5 Clock Distribution 5.1 Introduction The MCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory. The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. The primary clocks for the system are generated from the MCGOUTCLK clock.
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Clock definitions OSC MCG SIM Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers — MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx SIM MCG MCGIRCLK CG 32 kHz IRC MCGFFCLK FLL OUTDIV1 CG Core / system clocks OUTDIV2 CG Bus clock OUTDIV3 CG FlexBus clock OUTDIV4 CG Flash clock MCGOUTCLK PLL MCGFLLCLK FRDIV MCGPLLCLK MCGPLLCLK/ MCGFLLCLK System oscillator EXTAL0 OSCCLK XTAL_CLK XTAL0 EXTAL32 XTAL32 OSC logic Clock options for some peripherals (see note)
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Chapter 5 Clock Distribution Clock name Description System clock MCGOUTCLK divided by OUTDIV1 clocks the crossbar switch and bus masters directly connected to the crossbar. In addition, this clock is used for UART0 and UART1.
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Clock definitions Table 5-1.
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Chapter 5 Clock Distribution 5.5 Internal clocking requirements The clock dividers are programmed via the SIM module’s CLKDIV registers. Each divider is programmable from a divide-by-1 through divide-by-16 setting. The following requirements must be met when configuring the clocks for this device: 1. The core and system clock frequencies must be 72 MHz or slower. 2. The bus clock frequency must be programmed to 50 MHz or less and an integer divide of the core clock. 3.
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Clock Gating FTFL_FOPT [LPBOOT] Core/system clock Bus clock FlexBus clock Flash clock Description 0 0x7 (divide by 8) 0x7 (divide by 8) 0xF (divide by 16) 0xF (divide by 16) Low power boot 1 0x0 (divide by 1) 0x0 (divide by 1) 0x1 (divide by 2) 0x1 (divide by 2) Fast clock boot This gives the user flexibility for a lower frequency, low-power boot option.
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Chapter 5 Clock Distribution Table 5-2.
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Module clocks Table 5-2.
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Chapter 5 Clock Distribution 5.7.3 Debug trace clock The debug trace clock source can be clocked as shown in the following figure. MCGOUTCLK TRACECLKIN Debug Core / system clock SIM_SOPT2[TRACECLKSEL] Figure 5-3. Trace clock generation 5.7.4 PORT digital filter clocking The digital filters in each of the PORTx modules can be clocked as shown in the following figure. NOTE In stop mode, the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source.
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Module clocks 5.7.5 LPTMR clocking The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. MCGIRCLK LPO LPTMRx prescaler/glitch filter clock ERCLK32K OSCERCLK LPTMRx_PSR[PCS] Figure 5-5. LPTMRx prescaler/glitch filter clock generation 5.7.
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Chapter 5 Clock Distribution NOTE The MCGFLLCLK does not meet the USB jitter specifications for certification. 5.7.7 FlexCAN clocking The clock for the FlexCAN's protocol engine can be selected as shown in the following figure. OSCERCLK FlexCAN clock Bus clock CANx_CTRL1[CLKSRC] Figure 5-7. FlexCAN clock generation 5.7.8 UART clocking UART0 and UART1 modules operate from the core/system clock, which provides higher performance level for these modules. All other UART modules operate from the bus clock.
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Module clocks The I2S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can be generated internally from the audio master clock or supplied externally. The module also supports the option for synchronous operation between the receiver and transmitterproduct. The transmitter and receiver can independently select between the bus clock and the audio master clock to generate the bit clock. The MCLK and BCLK source options appear in the following figure.
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Chapter 5 Clock Distribution LPO TSI clock in low-power mode ERCLK32K TSI_GENCS[LPCLKS] Figure 5-10. TSI low-power clock generation K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Module clocks K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 176 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1.
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Reset 6.2 Reset This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (VPOR), the POR circuit causes a POR reset condition.
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Chapter 6 Reset and Boot Note that the nTRST signal is initially configured as disabled, however once configured to its JTAG functionality its associated input pin is configured as: • nTRST in PU 6.2.2.1 External pin reset (PIN) On this device, RESET is a dedicated pin. This pin is open drain and has an internal pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the RCM's SRS0[PIN] bit is set. 6.2.2.1.
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Reset 6.2.2.2 Low-voltage detect (LVD) The chip includes a system for managing low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip voltage. The LVD system is always enabled in normal run, wait, or stop mode. The LVD system is disabled when entering VLPx, LLS, or VLLSx modes.
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Chapter 6 Reset and Boot 6.2.2.5 Multipurpose clock generator loss-of-clock (LOC) The MCG module supports an external reference clock. If the C6[CME] bit in the MCG module is set, the clock monitor is enabled. If the external reference falls below floc_low or floc_high, as controlled by the C2[RANGE] field in the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this reset source.
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Reset 6.2.2.9 Lockup reset (LOCKUP) The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware. The LOCKUP condition causes a system reset and also causes the RCM's SRS1[LOCKUP] bit to set. 6.2.2.10 EzPort reset The EzPort supports a system reset request via EzPort signaling.
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Chapter 6 Reset and Boot 6.2.3.2 POR Only The POR Only reset asserts on the POR reset source only. It resets the PMC and System Register File. The POR Only reset also causes all other reset types (except VBAT POR) to occur. 6.2.3.3 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of the SMC and SIM. It also resets the LPTMR.
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Reset 6.2.3.7 Chip Reset Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET pin has also negated. It resets the remaining modules (the modules not reset by other reset types). 6.2.4 Reset Pin For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed.
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Chapter 6 Reset and Boot 6.2.5.3 Resetting the Debug subsystem Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ bit does not reset all debug-related registers.
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Boot The device can be in single chip (default) or serial flash programming mode (EzPort). While in single chip mode the device can be in run or various low power modes mentioned in Power mode transitions. Table 6-2. Mode select decoding EzPort chip select (EZP_CS) Description 0 Serial flash programming mode (EzPort) 1 Single chip (default) 6.3.3 FOPT boot options The flash option register (FOPT) in flash memory module (FTFL) allows the user to customize the operation of the MCU at boot time.
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Chapter 6 Reset and Boot Table 6-3. Flash Option Register (FTFL_FOPT) Bit Definitions (continued) Bit Num 0 Field LPBOOT Value Definition 0 Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at reset exit for higher divide values that produce lower power consumption at reset exit.
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Boot 6. At release of system reset, clocking is switched to a slow clock if the FOPT[LPBOOT] field in the Flash Memory module is configured for Low Power Boot 7. When the system exits reset, the processor sets up the stack, program counter (PC), and link register (LR). The processor reads the start SP (SP_main) from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR is set to 0xFFFF_FFFF. The CPU begins execution at the PC location.
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Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Power modes The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed.
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Power modes Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method Normal Wait via WFI Allows peripherals to function while the core is in sleep mode, reducing power. NVIC remains sensitive to interrupts; peripherals continue to be clocked. Sleep Interrupt Normal Stop via WFI Places chip in static state. Lowest power mode that retains all registers while maintaining LVD protection.
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Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode BAT (backup battery only) Description Core mode Normal recovery method Off Power-up Sequence The chip is powered down except for the VBAT supply. The RTC and the 32-byte VBAT register file for customer-critical data remain powered. 1. Resumes normal run mode operation by executing the LLWU interrupt service routine. 2. Follows the reset flow with the LLWU interrupt flag set for the NVIC. 7.
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Power mode transitions 7.4 Power mode transitions The following figure shows the power mode transitions. Any reset always brings the chip back to the normal run state. In run, wait, and stop modes active power regulation is enabled. The VLPx modes are limited in frequency, but offer a lower power operating mode than normal modes. The LLS and VLLSx modes are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application.
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Chapter 7 Power Management 7.5 Power modes shutdown sequencing When entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state. All low-power entry sequences are initiated by the core executing an WFI instruction.
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Module Operation in Low Power Modes • powered = Memory is powered to retain contents. • low power = Flash has a low power state that retains configuration registers to support faster wakeup. • OFF = Modules are powered off; module is in reset state upon wakeup. • wakeup = Modules can serve as a wakeup source for the chip. Table 7-2.
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Chapter 7 Power Management Table 7-2.
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Clock Gating 6. RTC_CLKOUT is not available. 7. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS or VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS, LLS, or VLLSx modes. 8. TSI wakeup from LLS and VLLSx modes is limited to a single selectable pin. 7.
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Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits. The MCU, in turn, confirms the security request and limits access to flash resources.
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Security Interactions with other Modules 8.3 Security Interactions with other Modules The flash security settings are used by the SoC to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. 8.3.1 Security interactions with FlexBus When flash security is enabled, SIM_SOPT2[FBSL] enables/disables off-chip accesses through the FlexBus interface.
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Chapter 8 Security When mass erase is disabled, mass erase via the debugger is blocked. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Security Interactions with other Modules K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 200 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. Four debug interfaces are supported: • • • • IEEE 1149.1 JTAG IEEE 1149.7 JTAG (cJTAG) Serial Wire Debug (SWD) ARM Real-Time Trace Interface(1-pin asynchronous mode only) The basic Cortex-M4 debug architecture is very flexible.
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Introduction INTNMI INTISR[239:0] SLEEPING Cortex-M4 Interrupts Sleep NVIC Core ETM Debug SLEEPDEEP Instr. Trigger Data TPIU AWIC Trace port (serial wire or multi-pin) MCM FPB DWT ITM Private Peripheral Bus (internal) ROM Table APB i/f I-code bus Bus Matrix SW/ JTAG SWJ-DP D-code bus Code bus System bus AHB-AP MDM-AP Figure 9-1. Cortex-M4 Debug Topology The following table presents a brief description of each one of the debug components. Table 9-1.
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Chapter 9 Debug Table 9-1. Debug Components Description (continued) Module FPB (Flash Patch and Breakpoints) Description The FPB implements hardware breakpoints and patches code and data from code space to system space. The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space.
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The Debug Port IR==BYPASSor IDCODE 4’b1111 or 4’b0000 jtag_updateinstr[3:0] A TDI nTRST TCK TMS TDO TRACESWO TDO TDI TDO TDI (1’b1 = 4-pin JTAG) (1’b0 = 2-pin cJTAG) To Test Resources CJTAG TDI TDO PEN TDO TDI nSYS_TDO nSYS_TDI nTRST 1’b1 SWCLKTCK TCK JTAGC nSYS_TRST TCK TMS_OUT TMS_OUT_OE SWDITMS nSYS_TCK nSYS_TMS AHB-AP JTAGir[3:0] TMS_IN IR==BYPASSor IDCODE JTAGNSW A DAP Bus 4’b1111 or 4’b1110 MDM-AP TMS SWDO SWDOEN SWDSEL JTAGSEL SWDITMS SWCLKTCK SWD/ JTAG SELECT Figure
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Chapter 9 Debug 2. Set the control level to 2 via zero-bit scans 3. Execute the Store Format (STFMT) command (00011) to set the scan format register to 1149.7 scan format 9.3 Debug Port Pin Descriptions The debug port pins default after POR to their JTAG functionality with the exception of JTAG_TRST_b and can be later reassigned to their alternate functionalities. In cJTAG and SWD modes JTAG_TDI and JTAG_TRST_b can be configured to alternate GPIO functions. Table 9-2.
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JTAG status and control registers 9.4.1 IR Codes Table 9-3.
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Chapter 9 Debug Table 9-4. MDM-AP Register Summary (continued) 0x0100_0000 Status See MDM-AP Status Register 0x0100_0004 Control See MDM-AP Control Register 0x0100_00FC ID Read-only identification register that always reads as 0x001C_0000 DPACC APACC A[3:2] RnW Debug Port 0x0C Data[31:0] Read Buffer (REBUFF) SWJ-DP See the ARM Debug Interface v5p1 Supplement.
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JTAG status and control registers 9.5.1 MDM-AP Control Register Table 9-5. MDM-AP Control register assignments Bit 0 Secure1 Name Flash Mass Erase in Progress Y Description Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN and SEC settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset. 1 Debug Disable N Set to disable debug.
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Chapter 9 Debug Table 9-5. MDM-AP Control register assignments (continued) Bit 7 Secure1 Name LLS, VLLSx Status Acknowledge N Description Set this bit to acknowledge the DAP LLS and VLLS Status bits have been read. This acknowledge automatically clears the status bits. This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger.
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Debug Resets Table 9-6. MDM-AP Status register assignments (continued) Bit 6 Name Backdoor Access Key Enable Description Indicates if the MCU has the backdoor access key enabled. 0 Disabled 1 Enabled 7 LP Enabled Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are the selected power mode the next time the ARM Core enters Deep Sleep. 0 Low Power Stop Mode is not enabled 1 Low Power Stop Mode is enabled Usage intended for debug operation in which Run to VLPS is attempted.
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Chapter 9 Debug • JTAG_TRST_b from an external signal. This signal is optional and may not be available in all packages. • Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the TCLK domain that allows the debugger to reset the debug logic. • TRST asserted via the cJTAG escape command.
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ITM 9.8 ITM The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can generate packets. If multiple sources generate packets at the same time, the ITM arbitrates the order in which packets are output. The four sources in decreasing order of priority are: 1.
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Chapter 9 Debug • It contains four comparators that you can configure as a hardware watchpoint, a PC sampler event trigger, or a data address sampler event trigger. The first comparator, DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. The second comparator, DWT_COMP1, can also be used as a data comparator.
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Debug & Security NOTE When using cJTAG and entering LLS mode, the cJTAG controller must be reset on exit from LLS mode. Going into a VLLSx mode causes all the debug controls and settings to be reset. To give time to the debugger to sync up with the HW, the MDM-AP Control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. 9.12.
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Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. The Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin. 10.
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Signal Multiplexing Integration Table 10-1. Reference links to related information (continued) Topic Related module Clocking Reference Clock Distribution Register access Peripheral bus controller Peripheral bridge 10.2.1 Port control and interrupt module features • Five 32-pin ports NOTE Not all pins are available on the device. See the following section for details. • Each 32-pin port is assigned one interrupt. • The digital filter option has two clock source options: bus clock and 1-kHz LPO.
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Chapter 10 Signal Multiplexing and Signal Descriptions 10.2.4 Signal multiplexing constraints 1. A given peripheral function must be assigned to a maximum of one package pin. Do not program the same function to more than one pin. 2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. 10.3 Pinout 10.3.
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Pinout 121 100 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 K1 18 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 K2 19 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 L1 20 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 L2 21 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 F5 22 VDDA VDDA VDDA G5 23 VR
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Chapter 10 Signal Multiplexing and Signal Descriptions 121 100 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 E5 40 VDD VDD VDD G3 41 VSS VSS VSS K8 42 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD0 FTM1_QD_ PHA L8 43 PTA13/ LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_ PHB K9 44 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_RX_ BCLK I2S0_TXD1 L9 45 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX
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Pinout 121 100 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 D9 64 PTB18 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_ BCLK FB_AD15 FTM2_QD_ PHA C9 65 PTB19 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FB_OE_b FTM2_QD_ PHB F10 66 PTB20 DISABLED PTB20 FB_AD31 CMP0_OUT F9 67 PTB21 DISABLED PTB21 FB_AD30 CMP1_OUT F8 68 PTB22 DISABLED PTB22 FB_AD29 CMP2_OUT E8 69 PTB23 DISABLED PTB23 B9 70 PTC0 ADC0_SE14/ TSI0_CH13 A
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Chapter 10 Signal Multiplexing and Signal Descriptions 121 100 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 C4 91 PTC17 DISABLED PTC17 UART3_TX FB_CS4_b/ FB_TSIZ0/ FB_BE31_24_ b B4 92 PTC18 DISABLED PTC18 UART3_RTS_ b FB_TBST_b/ FB_CS2_b/ FB_BE15_8_b A4 — PTC19 DISABLED PTC19 UART3_CTS_ b FB_CS3_b/ FB_BE7_0_b D4 93 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0 UART2_RTS_ b FB_ALE/ FB_CS1_b/ FB_TS_b D3 94 PTD1 ADC0_SE5b PTD1 SPI0_SCK UART2_C
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Pinout 10.3.2 K20 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 222 Preliminary General Business Information Freescale Semiconductor, Inc.
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PTD0/LLWU_P12 PTC18 PTC17 PTC16 VDD VSS PTC15 PTC14 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 PTC4/LLWU_P8 PTD1 94 76 PTD2/LLWU_P13 95 PTC6/LLWU_P10 PTD3 96 PTC5/LLWU_P9 PTD4/LLWU_P14 97 78 PTD5 77 PTD6/LLWU_P15 98 PTD7 100 99 Chapter 10 Signal Multiplexing and Signal Descriptions PTE0 1 75 VDD PTE1/LLWU_P0 2 74 VSS PTE2/LLWU_P1 3 73 PTC3/LLWU_P7 PTE3 4 72 PTC2 PTE4/LLWU_P2 5 71 PTC1/LLWU_P6
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Module Signal Description Tables 1 2 3 4 5 6 7 8 9 10 11 A PTD7 PTD5 PTD4/ LLWU_P14 PTC19 PTC14 PTC13 PTC8 PTC4/ LLWU_P8 NC NC NC A B NC PTD6/ LLWU_P15 PTD3 PTC18 PTC15 PTC12 PTC7 PTC3/ LLWU_P7 PTC0 PTB16 NC B C NC NC PTD2/ LLWU_P13 PTC17 PTC11/ LLWU_P11 PTC10 PTC6/ LLWU_P10 PTC2 PTB19 PTB11 NC C D NC NC PTD1 PTD0/ LLWU_P12 PTC16 PTC9 PTC5/ LLWU_P9 PTC1/ LLWU_P6 PTB18 PTB10 PTB8 D E NC PTE2/ LLWU_P1 PTE1/ LLWU_P0 PTE0 VDD VDD VDD PTB23
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Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.1 Core Modules Table 10-2. JTAG Signal Descriptions Chip signal name Module signal name Description I/O JTAG_TMS JTAG_TMS/ SWD_DIO JTAG Test Mode Selection I/O JTAG_TCLK JTAG_TCLK/ SWD_CLK JTAG Test Clock I JTAG_TDI JTAG_TDI JTAG Test Data Input I JTAG_TDO JTAG_TDO/ TRACE_SWO JTAG Test Data Output O JTAG_TRST JTAG_TRST_b JTAG Reset I Table 10-3.
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Module Signal Description Tables 10.4.2 System Modules Table 10-5. System Signal Descriptions Chip signal name Module signal name NMI — Description I/O Non-maskable interrupt I NOTE: Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin. RESET — Reset bi-directional signal I/O VDD — MCU power I VSS — MCU ground I Table 10-6.
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Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.4 Memories and Memory Interfaces Table 10-9. EzPort Signal Descriptions Chip signal name Module signal name Description I/O EZP_CLK EZP_CK EzPort Clock Input EZP_CS EZP_CS EzPort Chip Select Input EZP_DI EZP_D EzPort Serial Data In Input EZP_DO EZP_Q EzPort Serial Data Out Output Table 10-10.
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Module Signal Description Tables Table 10-10. FlexBus Signal Descriptions (continued) Chip signal name Module signal name FB_TS/ FB_ALE FB_TS Description I/O Transfer Start—Indicates that the chip has begun a bus transaction and that the address and attributes are valid. O An inverted FB_TS is available as an address latch enable (FB_ALE), which indicates when the address is being driven on the FB_AD bus. FB_TS/FB_ALE is asserted for one bus clock cycle.
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Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-10. FlexBus Signal Descriptions (continued) Chip signal name Module signal name FB_TA4 FB_TA Description Transfer Acknowledge—Indicates that the external data transfer is complete. When FB_TA is asserted during a read transfer, FlexBus latches the data and then terminates the transfer. When FB_TA is asserted during a write transfer, the transfer is terminated.
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Module Signal Description Tables Table 10-11. ADC 0 Signal Descriptions (continued) Chip signal name Module signal name ADC0_DM3, PGA0_DM, ADC0_DM[1:0] DADM3–DADM0 ADC0_SE[18,17,15:1 2,9:4] [18,17,15:12,9:4] AD23–AD4 VREFH Description I/O Differential Analog Channel Inputs I Single-Ended Analog Channel Inputs I VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select Low I VDDA VDDA Analog Power Supply I VSSA VSSA Analog Ground I Table 10-12.
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Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-15. CMP 2 Signal Descriptions Chip signal name Module signal name Description I/O CMP2_IN[5:0] IN[5:0] Analog voltage inputs I CMP2_OUT CMPO Comparator output O Table 10-16. DAC 0 Signal Descriptions Chip signal name Module signal name DAC0_OUT — Description I/O DAC output O Table 10-17.
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Module Signal Description Tables Table 10-20. FTM 2 Signal Descriptions Chip signal name Module signal name FTM_CLKIN[1:0] EXTCLK FTM2_CH[1:0] CHn FTM2_FLT0 FAULTj FTM2_QD_PHA FTM2_QD_PHB Description I/O External clock. FTM external clock can be selected to drive the FTM counter. FTM channel (n), where n can be 7-0 I I/O Fault input (j), where j can be 3-0 I PHA Quadrature decoder phase A input. Input pin associated with quadrature decoder phase A. I PHB Quadrature decoder phase B input.
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Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.7 Communication Interfaces Table 10-25. USB FS OTG Signal Descriptions Chip signal name Module signal name Description I/O USB0_DM usb_dm USB D- analog data signal on the USB bus. I/O USB0_DP usb_dp USB D+ analog data signal on the USB bus. I/O USB_CLKIN — Alternate USB clock input I Table 10-26.
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Module Signal Description Tables Table 10-30. I2C 0 Signal Descriptions Chip signal name Module signal name I2C0_SCL SCL I2C0_SDA SDA Description I/O Bidirectional serial clock line of the I2C system. Bidirectional serial data line of the I2C system. I/O I/O Table 10-31. I2C 1 Signal Descriptions Chip signal name Module signal name Description I/O I2C1_SCL SCL Bidirectional serial clock line of the I2C system. I/O I2C1_SDA SDA Bidirectional serial data line of the I2C system.
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Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-35. UART 3 Signal Descriptions Chip signal name Module signal name Description I/O UART3_CTS CTS Clear to send I UART3_RTS RTS Request to send O UART3_TX TXD Transmit data O UART3_RX RXD Receive data I Table 10-36.
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Module Signal Description Tables Table 10-39. TSI 0 Signal Descriptions Chip signal name Module signal name TSI0_CH[15:0] TSI_IN[15:0] Description I/O TSI pins. Switchable driver that connects directly to the electrode pins TSI[15:0] can operate as GPIO pins I/O K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 236 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 11 Port control and interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 11.1.1 Overview The port control and interrupt (PORT) module provides support for port control, and external interrupt functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state. There is one instance of the PORT module for each port.
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Introduction • Individual drive strength field supporting high and low drive strength on selected pins • Individual slew rate field supporting fast and slow slew rates on selected pins • Individual input passive filter field supporting enable and disable of the individual input passive filter on selected pins • Individual open drain field supporting enable and disable of the individual open drain output on selected pins • Individual mux control field supporting analog or pin disabled, GPIO, and up to six c
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Chapter 11 Port control and interrupts (PORT) NOTE Not all pins within each port are implemented on each device. 11.1.3 Detailed signal description The following table contains the detailed signal description for the PORT interface. Table 11-2. PORT interface—detailed signal description Signal PORTx[31:0] I/O I/O Description External interrupt. State meaning Asserted—pin is logic one. Negated—pin is logic zero. Timing Assertion—may occur at any time and can assert asynchronously to the system clock.
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Introduction PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_9034 Pin Control Register n (PORTA_PCR13) 32 R/W See section 11.14.1/245 4004_9038 Pin Control Register n (PORTA_PCR14) 32 R/W See section 11.14.1/245 4004_903C Pin Control Register n (PORTA_PCR15) 32 R/W See section 11.14.1/245 4004_9040 Pin Control Register n (PORTA_PCR16) 32 R/W See section 11.14.
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Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_A034 Pin Control Register n (PORTB_PCR13) 32 R/W See section 11.14.1/245 4004_A038 Pin Control Register n (PORTB_PCR14) 32 R/W See section 11.14.1/245 4004_A03C Pin Control Register n (PORTB_PCR15) 32 R/W See section 11.14.1/245 4004_A040 Pin Control Register n (PORTB_PCR16) 32 R/W See section 11.14.
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Introduction PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_B034 Pin Control Register n (PORTC_PCR13) 32 R/W See section 11.14.1/245 4004_B038 Pin Control Register n (PORTC_PCR14) 32 R/W See section 11.14.1/245 4004_B03C Pin Control Register n (PORTC_PCR15) 32 R/W See section 11.14.1/245 4004_B040 Pin Control Register n (PORTC_PCR16) 32 R/W See section 11.14.
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Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_C034 Pin Control Register n (PORTD_PCR13) 32 R/W See section 11.14.1/245 4004_C038 Pin Control Register n (PORTD_PCR14) 32 R/W See section 11.14.1/245 4004_C03C Pin Control Register n (PORTD_PCR15) 32 R/W See section 11.14.1/245 4004_C040 Pin Control Register n (PORTD_PCR16) 32 R/W See section 11.14.
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Introduction PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_D034 Pin Control Register n (PORTE_PCR13) 32 R/W See section 11.14.1/245 4004_D038 Pin Control Register n (PORTE_PCR14) 32 R/W See section 11.14.1/245 4004_D03C Pin Control Register n (PORTE_PCR15) 32 R/W See section 11.14.1/245 4004_D040 Pin Control Register n (PORTE_PCR16) 32 R/W See section 11.14.
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Chapter 11 Port control and interrupts (PORT) 11.14.
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Introduction PORTx_PCRn field descriptions (continued) Field Description 1100 Interrupt when logic one. Others Reserved. 15 LK 14–11 Reserved 10–8 MUX Lock Register 0 1 Pin Control Register fields [15:0] are not locked. Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. This field is reserved. This read-only field is reserved and always has the value 0. Pin Mux Control Not all pins support all pin muxing slots.
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Chapter 11 Port control and interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description 2 SRE Slew Rate Enable This bit is read only for pins that do not support a configurable slew rate. Slew rate configuration is valid in all digital pin muxing modes. 0 1 1 PE Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
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Introduction 11.14.3 Global Pin Control High Register (PORTx_GPCHR) Only 32-bit writes are supported to this register.
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Chapter 11 Port control and interrupts (PORT) PORTx_ISFR field descriptions (continued) Field Description 0 1 Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag.
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Introduction The configuration of each pin control register is retained when the PORT module is disabled. 11.1.5.2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to sixteen pins, all with the same value. Registers that are locked cannot be written using the global pin control registers.
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Chapter 11 Port control and interrupts (PORT) The PORT module generates a single DMA request that asserts when the interrupt status flag is set for any enabled DMA request in that port. The DMA request negates after the DMA transfer is completed, because that clears the interrupt status flags for all enabled DMA requests. During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously set if the required level or edge is detected.
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Introduction K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 252 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 12 System Integration Module (SIM) 12.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The System Integration Module (SIM) provides system control and chip configuration registers. 12.1.
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Memory map and register definition 12.2 Memory map and register definition The SIM module contains many fields for selecting the clock source and dividers for various module clocks. See the Clock Distribution chapter for more information, including block diagrams and clock definitions. NOTE The SIM_SOPT1 and SIM_SOPT1CFG registers are located at a different base address than the other SIM registers.
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Chapter 12 System Integration Module (SIM) 12.2.1 System Options Register 1 (SIM_SOPT1) NOTE The SOPT1 register is only reset on POR or LVD.
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Memory map and register definition SIM_SOPT1 field descriptions (continued) Field Description 0 1 29 USBVSTBY USB voltage regulator in standby mode during VLPR and VLPW modes Controls whether the USB voltage regulator is placed in standby mode during VLPR and VLPW modes. 0 1 28–20 Reserved 19–18 OSC32KSEL USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
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Chapter 12 System Integration Module (SIM) 12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG) NOTE The SOPT1CFG register is reset on System Reset not VLLS.
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Memory map and register definition SIM_SOPT1CFG field descriptions (continued) Field Description 23–10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9–8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.2.
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Chapter 12 System Integration Module (SIM) SIM_SOPT2 field descriptions (continued) Field 18 USBSRC Description USB clock source select Selects the clock source for the USB 48 MHz clock. 0 1 17 Reserved 16 PLLFLLSEL This field is reserved. This read-only field is reserved and always has the value 0. PLL/FLL clock select Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral clocking options. 0 1 15–13 Reserved External bypass clock (USB_CLKIN).
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Memory map and register definition SIM_SOPT2 field descriptions (continued) Field Description 110 111 OSCERCLK0 Reserved 4 RTC clock out select RTCCLKOUTSEL Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the RTC_CLKOUT pin. 0 1 3–0 Reserved RTC 1 Hz clock is output on the RTC_CLKOUT pin. RTC 32.768kHz clock is output on the RTC_CLKOUT pin. This field is reserved. This read-only field is reserved and always has the value 0. 12.2.
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Chapter 12 System Integration Module (SIM) SIM_SOPT4 field descriptions (continued) Field Description 0 1 27 Reserved 26 FTM2CLKSEL HSCMP0 output drives FTM0 hardware trigger 0 FTM1 channel match drives FTM0 hardware trigger 0 This field is reserved. This read-only field is reserved and always has the value 0. FlexTimer 2 External Clock Pin Select Selects the external pin used to drive the clock to the FTM2 module.
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Memory map and register definition SIM_SOPT4 field descriptions (continued) Field 17–9 Reserved 8 FTM2FLT0 Description This field is reserved. This read-only field is reserved and always has the value 0. FTM2 Fault 0 Select Selects the source of FTM2 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate PORTx pin control register. 0 1 7–5 Reserved 4 FTM1FLT0 FTM2_FLT0 pin CMP0 out This field is reserved.
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Chapter 12 System Integration Module (SIM) 12.2.
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Memory map and register definition 12.2.
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Chapter 12 System Integration Module (SIM) SIM_SOPT7 field descriptions (continued) Field Description 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PIT trigger 2 PIT trigger 3 FTM0 trigger FTM1 trigger FTM2 trigger Unused RTC alarm RTC seconds Low-power timer trigger Unused 7 ADC0 alternate trigger enable ADC0ALTTRGEN Enable alternative conversion triggers for ADC0. 0 1 6–5 Reserved PDB trigger selected for ADC0. Alternate trigger selected for ADC0. This field is reserved.
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Memory map and register definition 12.2.7 System Device Identification Register (SIM_SDID) Address: 4004_7000h base + 1024h offset = 4004_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 x* x* x* x* x* x* x* REVID R FAMID PINID W Reset x* x* x* x* x* x* x* x* x* * Notes: • x = Undefined at reset.
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Chapter 12 System Integration Module (SIM) SIM_SDID field descriptions (continued) Field Description 3–0 PINID Pincount identification Specifies the pincount of the device. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved Reserved Reserved Reserved Reserved 64-pin 80-pin 81-pin 100-pin Reserved Reserved Reserved Reserved Reserved Reserved Reserved 12.2.
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Memory map and register definition SIM_SCGC1 field descriptions (continued) Field Description 23–22 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 21 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 20–12 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 11 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 12 System Integration Module (SIM) SIM_SCGC2 field descriptions Field Description 31–14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12 DAC0 DAC0 Clock Gate Control This bit controls the clock gate to the DAC0 module. 0 1 Clock disabled Clock enabled 11–1 Reserved This field is reserved.
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Memory map and register definition SIM_SCGC3 field descriptions (continued) Field Description 0 1 Clock disabled Clock enabled 26 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 25 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 24 FTM2 FTM2 Clock Gate Control This bit controls the clock gate to the FTM2 module. 0 1 Clock disabled Clock enabled 23–18 Reserved This field is reserved.
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Chapter 12 System Integration Module (SIM) SIM_SCGC4 field descriptions Field Description 31–28 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 27–21 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 20 VREF VREF Clock Gate Control This bit controls the clock gate to the VREF module. 0 1 19 CMP Comparator Clock Gate Control This bit controls the clock gate to the comparator module.
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Memory map and register definition SIM_SCGC4 field descriptions (continued) Field Description 7 I2C1 I2C1 Clock Gate Control This bit controls the clock gate to the I 2 C1 module. 0 1 6 I2C0 Clock disabled Clock enabled I2C0 Clock Gate Control This bit controls the clock gate to the I 2 C0 module. 0 1 Clock disabled Clock enabled 5–4 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 3 Reserved This field is reserved.
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Chapter 12 System Integration Module (SIM) SIM_SCGC5 field descriptions Field Description 31–19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 17–14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13 PORTE Port E Clock Gate Control This bit controls the clock gate to the Port E module.
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Memory map and register definition SIM_SCGC5 field descriptions (continued) Field Description 1 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 0 LPTIMER Low Power Timer Access Control This bit controls software access to the Low Power Timer module. 0 1 Access disabled Access enabled 12.2.
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Chapter 12 System Integration Module (SIM) SIM_SCGC6 field descriptions (continued) Field Description 0 1 26 Reserved 25 FTM1 This field is reserved. This read-only field is reserved and always has the value 0. FTM1 Clock Gate Control This bit controls the clock gate to the FTM1 module. 0 1 24 FTM0 This bit controls the clock gate to the FTM0 module. This bit controls the clock gate to the PIT module. This bit controls the clock gate to the PDB module.
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Memory map and register definition SIM_SCGC6 field descriptions (continued) Field 14 Reserved 13 SPI1 Description This field is reserved. This read-only field is reserved and always has the value 0. SPI1 Clock Gate Control This bit controls the clock gate to the SPI1 module. 0 1 12 SPI0 Clock disabled Clock enabled SPI0 Clock Gate Control This bit controls the clock gate to the SPI0 module. 0 1 Clock disabled Clock enabled 11–10 Reserved This field is reserved.
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Chapter 12 System Integration Module (SIM) 12.2.
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Memory map and register definition 12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1) NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode.
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Chapter 12 System Integration Module (SIM) SIM_CLKDIV1 field descriptions (continued) Field Description 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 23–20 OUTDIV3 Clock 3 output divider value This field sets the divide value for the FlexBus clock driven to the external pin (FB_CLK). At the end of reset, it is loaded with either 0001 or 1111 depending on FTFL_FOPT[LPBOOT]. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 19–16 OUTDIV4 Divide-by-4.
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Memory map and register definition SIM_CLKDIV1 field descriptions (continued) Field Description 1001 1010 1011 1100 1101 1110 1111 15–0 Reserved Divide-by-10. Divide-by-11. Divide-by-12. Divide-by-13. Divide-by-14. Divide-by-15. Divide-by-16. This field is reserved. This read-only field is reserved and always has the value 0. 12.2.
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Chapter 12 System Integration Module (SIM) 12.2.17 Flash Configuration Register 1 (SIM_FCFG1) The reset value of EESIZE and DEPART are based on user programming in user IFR via the PGMPART flash command.
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Memory map and register definition SIM_FCFG1 field descriptions (continued) Field Description This field specifies the amount of program flash memory available on the device . Undefined values are reserved. 0101 0111 1001 23–20 Reserved 19–16 EESIZE 64 KB of program flash memory, 2 KB protection region 128 KB of program flash, 4 KB protection region 256 KB of program flash, 8 KB protection region This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 12 System Integration Module (SIM) 12.2.
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Memory map and register definition SIM_FCFG2 field descriptions (continued) Field Description This field concatenated with leading zeros plus the FlexNVM base address indicates the first invalid address of the FlexNVM (flash block 1). For example, if MAXADDR1 = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value for a device with 256 KB FlexNVM. 15–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.
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Chapter 12 System Integration Module (SIM) 12.2.21 Unique Identification Register Mid Low (SIM_UIDML) Address: 4004_7000h base + 105Ch offset = 4004_805Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID R W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* * Notes: • Reset value loaded during System Reset from Flash IFR.
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Functional description K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 286 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 13 Reset Control Module (RCM) 13.1 Introduction This chapter describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. 13.2 Reset memory map and register descriptions The Reset Control Module (RCM) registers provide reset status information and reset filter control.
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Reset memory map and register descriptions • • • • LVD (without POR) — 0x02 VLLS mode wakeup due to RESET pin assertion — 0x41 VLLS mode wakeup due to other wakeup sources — 0x01 Other reset — a bit is set if its corresponding reset source caused the reset Address: 4007_F000h base + 0h offset = 4007_F000h Bit Read 7 6 5 4 3 2 1 0 POR PIN WDOG 0 LOL LOC LVD WAKEUP 1 0 0 0 0 0 1 0 Write Reset RCM_SRS0 field descriptions Field 7 POR Description Power-On Reset Indicates a reset ha
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Chapter 13 Reset Control Module (RCM) RCM_SRS0 field descriptions (continued) Field Description 0 1 1 LVD Low-Voltage Detect Reset If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is also set by POR. 0 1 0 WAKEUP Reset not caused by a loss of external clock. Reset caused by a loss of external clock.
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Reset memory map and register descriptions RCM_SRS1 field descriptions (continued) Field Description 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 SACKERR Stop Mode Acknowledge Error Reset Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode.
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Chapter 13 Reset Control Module (RCM) NOTE The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled or when entering any low leakage stop mode . Address: 4007_F000h base + 4h offset = 4007_F004h Bit Read Write Reset 7 6 5 4 3 0 0 0 0 2 RSTFLTSS 0 0 0 1 0 RSTFLTSRW 0 0 1 0 0 0 RCM_RPFC field descriptions Field 7–3 Reserved 2 RSTFLTSS Description This field is reserved. This read-only field is reserved and always has the value 0.
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Reset memory map and register descriptions RCM_RPFW field descriptions Field 7–5 Reserved 4–0 RSTFLTSEL Description This field is reserved. This read-only field is reserved and always has the value 0. Reset Pin Filter Bus Clock Select Selects the reset pin bus clock filter width.
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Chapter 13 Reset Control Module (RCM) 13.2.5 Mode Register (RCM_MR) This register includes read-only status flags to indicate the state of the mode pins during the last Chip Reset. Address: 4007_F000h base + 7h offset = 4007_F007h Bit 7 6 5 Read 4 3 2 0 1 0 EZP_MS 0 0 0 Write Reset 0 0 0 0 0 0 RCM_MR field descriptions Field Description 7–2 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
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Reset memory map and register descriptions K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 294 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 14 System Mode Controller 14.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The system mode controller (SMC) is responsible for sequencing the system into and out of all low power stop and run modes. Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode.
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Modes of operation ARM CPU mode MCU mode Sleep Wait Deep Sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Freescale MCU documentation normally uses wait and stop. In addition, Freescale MCUs also augment stop, wait, and run modes in a number of ways. The power management controller (PMC) contains a run and a stop mode regulator. Run regulation is used in normal run, wait and stop modes.
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Chapter 14 System Mode Controller Table 14-1. Power modes (continued) Mode Description VLLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic. All system RAM contents are retained and I/O states are held. FlexRAM contents are not retained. Internal logic states are not retained. VLLS2 The core clock is gated off.
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Memory map and register descriptions If the MCU is configured for a disallowed or reserved power mode, the MCU remains in its current power mode. For example, if the MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and the RUNM bits remain 00b, indicating the MCU is still in Normal Run mode. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS.
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Chapter 14 System Mode Controller 14.3.2 Power Mode Control register (SMC_PMCTRL) The PMCTRL register controls entry into low-power run and stop modes, provided that the selected power mode is allowed via an appropriate setting of the protection (PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information.
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Memory map and register descriptions SMC_PMCTRL field descriptions (continued) Field 2–0 STOPM Description Stop Mode Control When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. After any system reset, this field is cleared by hardware on any successful write to the PMPROT register.
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Chapter 14 System Mode Controller SMC_VLLSCTRL field descriptions (continued) Field 3 Reserved 2–0 VLLSM Description This field is reserved. This read-only field is reserved and always has the value 0. VLLS Mode Control Controls which VLLS sub-mode to enter if STOPM=VLLS. 000 001 010 011 100 101 110 111 Reserved VLLS1 VLLS2 VLLS3 Reserved Reserved Reserved Reserved 14.3.4 Power Mode Status register (SMC_PMSTAT) PMSTAT is a read-only, one-hot register which indicates the current power mode of the system.
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Functional description SMC_PMSTAT field descriptions (continued) Field Description 001_0000 010_0000 100_0000 Current power mode is VLPS Current power mode is LLS Current power mode is VLLS 14.4 Functional description 14.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal run state. K20 Sub-Family Reference Manual, Rev. 1.
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Chapter 14 System Mode Controller Any reset VLPW 4 5 1 VLPR WAIT 3 RUN 6 7 2 STOP VLPS 10 8 9 VLLSx LLS 11 Figure 14-5. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 14-7. Power mode transition triggers Transition # From To 1 RUN WAIT Trigger conditions Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note.
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Functional description Table 14-7. Power mode transition triggers (continued) Transition # From To 2 RUN STOP Trigger conditions PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 3 STOP RUN Interrupt or Reset RUN VLPR Reduce system, bus and core frequency to 2 MHz or less, Flash access limited to 1 MHz. Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10.
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Chapter 14 System Mode Controller Table 14-7. Power mode transition triggers (continued) Transition # From To 10 RUN LLS PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. LLS RUN Wakeup from enabled LLWU input source or RESET pin.
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Functional description Reset Control Module LowLeakage Wakeup CPU (RCM) (LLWU) Stop/Wait LP exit LP exit System Mode Controller CCM low power bus (SMC) Clock Control Module Bus masters low power bus (non-CPU) Bus slaves low power bus (CCM) PMC low power bus Flash low power bus MCG enable System Power (PMC) System Clocks (MCG) Flash Memory Module Figure 14-6. Low-power system components and connections 14.4.2.
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Chapter 14 System Mode Controller 14.4.2.2 Stop mode exit sequence Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR): 1. The on-chip regulator in the PMC and internal power switches are restored. 2. Clock generators are enabled in the MCG. 3. System and bus clocks are enabled to all masters and slaves. 4.
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Functional description 14.4.3 Run modes The device contains two different run modes: • Run • Very Low-Power Run (VLPR) 14.4.3.1 RUN mode This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR): • The processor reads the start SP (SP_main) from vector-table offset 0x000 • The processor reads the start PC from vector-table offset 0x004 • LR is set to 0xFFFF_FFFF.
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Chapter 14 System Mode Controller in the MCG module, the module clock enables in the SIM, or any clock divider registers. To reenter Normal Run mode, clear RUNM. The PMSTAT register is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode.
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Functional description VLPR mode restrictions also apply to VLPW. When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. A system reset will cause an exit from VLPW mode, returning the device to normal RUN mode. 14.4.5 Stop modes This device contains a variety of stop modes to meet your application needs.
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Chapter 14 System Mode Controller A module capable of providing an asynchronous interrupt to the device takes the device out of STOP mode and returns the device to normal RUN mode. Refer to the device's Power Management chapter for peripheral, I/O, and memory operation in STOP mode. When an interrupt request occurs, the CPU exits STOP mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine.
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Functional description Before entering LLS mode, the user should configure the low-leakage wakeup (LLWU) module to enable the desired wakeup sources. The available wakeup sources in LLS are detailed in the chip configuration details for this device. After wakeup from LLS, the device returns to normal RUN mode with a pending LLWU module interrupt. In the LLWU interrupt service routine (ISR), the user can poll the LLWU module wakeup flags to determine the source of the wakeup.
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Chapter 14 System Mode Controller When entering VLLS, each I/O pin is latched as configured before executing VLLS. Because all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS. This information must be restored before the ACKISO bit in the PMC is set. An asserted RESET pin will cause an exit from any VLLS mode, returning the device to normal RUN mode.
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Functional description The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge (VLLDBGACK) bit that is set to release the ARM core being held in reset following a VLLS recovery. The debugger reinitializes all debug IP, and then asserts the VLLDBGACK control bit to allow the RCM to release the ARM core from reset and allow CPU operation to begin.
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Chapter 15 Power Management Controller 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system. 15.
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Low-voltage detect (LVD) system • The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF bit is set when the supply voltage falls below the selected trip point (VLVD). The LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal supply has returned above the trip point; otherwise, the LVDF bit remains set. • The low voltage warning flag (LVWF) operates in a level sensitive manner.
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Chapter 15 Power Management Controller 15.4 I/O retention When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode. The I/O are released immediately after a wakeup or reset event. In the case of LLS exit via a RESET pin, the I/O default to their reset state.
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Memory map and register descriptions While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect systems that must have LVD always on, configure the SMC's power mode protection register (PMPROT) to disallow any very low power or low leakage modes from being enabled. See the device's data sheet for the exact LVD trip voltages. NOTE The LVDV bits are reset solely on a POR Only event.
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Chapter 15 Power Management Controller PMC_LVDSC1 field descriptions (continued) Field Description 00 01 10 11 Low trip point selected (V LVD = V LVDL ) High trip point selected (V LVD = V LVDH ) Reserved Reserved 15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) This register contains status and control bits to support the low voltage warning function. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC2 settings.
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Memory map and register descriptions PMC_LVDSC2 field descriptions (continued) Field 5 LVWIE Description Low-Voltage Warning Interrupt Enable Enables hardware interrupt requests for LVWF. 0 1 4–2 Reserved 1–0 LVWV Hardware interrupt disabled (use polling) Request a hardware interrupt when LVWF = 1 This field is reserved. This read-only field is reserved and always has the value 0. Low-Voltage Warning Voltage Select Selects the LVW trip point voltage (VLVW).
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Chapter 15 Power Management Controller PMC_REGSC field descriptions (continued) Field Description BGEN controls whether the bandgap is enabled in lower power modes of operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage reference in low power modes of operation, set BGEN to continue to enable the bandgap operation. NOTE: When the bandgap voltage reference is not needed in low power modes, clear BGEN to avoid excess power consumption.
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Memory map and register descriptions K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 322 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The LLWU module allows the user to select up to 16 external pin sources and up to 8 internal modules as a wakeup source from low-leakage power modes. The input sources are described in the device's chip configuration details. Each of the available wakeup sources can be individually enabled.
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Introduction • External pin wakeup inputs, each of which is programmable as falling-edge, risingedge, or any change • Wakeup inputs that are activated if enabled after MCU enters a low-leakage power mode • Optional digital filters provided to qualify an external pin detect and RESET pin detect. 16.1.2 Modes of operation The LLWU module becomes functional on entry into a low-leakage power mode. After recovery from LLS, the LLWU is immediately disabled.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) When theRESET pin filter or wakeup pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within 5 LPO clock cycles of an active edge, the edge event will be detected by the LLWU. For RESET pin filtering, this means that there is no restart to the minimum LPO cycle duration as the filtering transitions from a non-low leakage filter, which is implemented in the RCM, to the LLWU filter. 16.1.2.
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LLWU signal descriptions enter low leakge mode WUME7 Interrupt module flag detect Module7 interrupt flag (LLWU_M7IF) LLWU_MWUF7 occurred Internal module sources Interrupt module flag detect Module0 interrupt flag (LLWU_M0IF) FILT1[FILTSEL] LLWU_MWUF0 occurred WUME0 LPO LLWU_P15 Synchronizer LLWU_P0 Edge detect Pin filter 1 LPO Synchronizer FILT1[FILTE] Pin filter 1 wakeup occurred LLWU controller FILT2[FILTE] Edge detect Pin filter 2 exit low leakge mode Pin filter 2 wakeup occurred in
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.
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Memory map/register definition 16.3.1 LLWU Pin Enable 1 register (LLWU_PE1) LLWU_PE1 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P3-LLWU_P0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_PE1 field descriptions (continued) Field Description 10 11 External input pin enabled with falling edge detection External input pin enabled with any change detection 16.3.2 LLWU Pin Enable 2 register (LLWU_PE2) LLWU_PE2 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P7-LLWU_P4. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS.
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Memory map/register definition LLWU_PE2 field descriptions (continued) Field Description 10 11 1–0 WUPE4 External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P4 Enables and configures the edge detection for the wakeup pin.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_PE3 field descriptions (continued) Field Description 10 11 3–2 WUPE9 Wakeup Pin Enable For LLWU_P9 Enables and configures the edge detection for the wakeup pin.
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Memory map/register definition LLWU_PE4 field descriptions (continued) Field Description 10 11 5–4 WUPE14 Wakeup Pin Enable For LLWU_P14 Enables and configures the edge detection for the wakeup pin.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_ME field descriptions Field 7 WUME7 Description Wakeup Module Enable For Module 7 Enables an internal module as a wakeup source input. 0 1 6 WUME6 Wakeup Module Enable For Module 6 Enables an internal module as a wakeup source input. 0 1 5 WUME5 Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input.
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Memory map/register definition 16.3.6 LLWU Flag 1 register (LLWU_F1) LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F1 field descriptions (continued) Field 4 WUF4 Description Wakeup Flag For LLWU_P4 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF4. 0 1 3 WUF3 Wakeup Flag For LLWU_P3 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF3.
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Memory map/register definition NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F2 field descriptions (continued) Field Description Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF10. 0 1 1 WUF9 Wakeup Flag For LLWU_P9 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF9.
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Memory map/register definition LLWU_F3 field descriptions Field 7 MWUF7 Description Wakeup flag For module 7 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 6 MWUF6 Wakeup flag For module 6 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_F3 field descriptions (continued) Field Description Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 Module 0 input was not a wakeup source Module 0 input was a wakeup source 16.3.
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Memory map/register definition LLWU_FILT1 field descriptions (continued) Field 3–0 FILTSEL Description Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 ... 1111 Select LLWU_P0 for filter ... Select LLWU_P15 for filter 16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2) LLWU_FILT2 is a control and status register that is used to enable/disable the digital filter 2 features for an external pin.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) LLWU_FILT2 field descriptions (continued) Field 3–0 FILTSEL Description Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 ... 1111 Select LLWU_P0 for filter ... Select LLWU_P15 for filter 16.3.11 LLWU Reset Enable register (LLWU_RST) LLWU_RST is a control register that is used to enable/disable the digital filter for the external pin detect and RESET pin.
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Functional description 16.4 Functional description This on-chip peripheral module is called a low-leakage wakeup unit (LLWU) module because it allows internal peripherals and external input pins as a source of wakeup from low-leakage modes. It is operational only in LLS and VLLSx modes. The LLWU module contains pin enables for each external pin and internal module. For each external pin, the user can disable or select the edge type for the wakeup.
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Chapter 16 Low-Leakage Wakeup Unit (LLWU) 16.4.2 VLLS modes In the case of a wakeup due to external pin or internal module wakeup, recovery is always via a reset flow and the RCM_SRS[WAKEUP] is set indicating the low-leakage mode was active. State retention data is lost and I/O will be restored after PMC_REGSC[ACKISO] has been written. A VLLS exit event due to RESET pin assertion causes an exit via a system reset. State retention data is lost and the I/O states immediately return to their reset state.
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Functional description K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 344 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 17 Miscellaneous Control Module (MCM) 17.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 17.1.1 Features The MCM includes the following features: • Program-visible information on the platform configuration and revision 17.
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Memory map/register descriptions 17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the device’s crossbar switch. Address: E008_0000h base + 8h offset = E008_0008h Bit 15 14 13 12 Read 11 10 9 8 7 6 5 4 0 3 2 1 0 1 1 1 1 ASC Write Reset 0 0 0 0 0 0 0 0 0 0 0 1 MCM_PLASC field descriptions Field Description 15–8 Reserved This field is reserved.
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Chapter 17 Miscellaneous Control Module (MCM) MCM_PLAMC field descriptions (continued) Field Description 0 1 A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present 17.2.3 Control Register (MCM_CR) CR defines the arbitration and protection schemes for the two system RAM arrays. NOTE Bits 23-0 are undefined after reset.
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Memory map/register descriptions MCM_CR field descriptions (continued) Field Description Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the SRAM_L array. 00 01 10 11 27 Reserved Round robin Special round robin (favors SRAM backoor accesses over the processor) Fixed priority. Processor has highest, backdoor has lowest Fixed priority. Backdoor has highest, processor has lowest This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 18 Crossbar Switch (AXBS) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure.
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Memory Map / Register Definition 18.2 Memory Map / Register Definition Each slave port of the crossbar switch contains configuration registers. Read- and writetransfers require two bus clock cycles. The registers can be read from and written to only in supervisor mode. Additionally, these registers can be read from or written to only by 32-bit accesses. A bus error response is returned if an unimplemented location is accessed within the crossbar switch.
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Chapter 18 Crossbar Switch (AXBS) AXBS memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4000_4710 Control Register (AXBS_CRS7) 32 R/W 0000_0000h 18.2.2/354 4000_4800 Master General Purpose Control Register (AXBS_MGPCR0) 32 R/W 0000_0000h 18.2.3/356 4000_4900 Master General Purpose Control Register (AXBS_MGPCR1) 32 R/W 0000_0000h 18.2.
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Memory Map / Register Definition * Notes: • See the device configuration details for the reset value of this register. AXBS_PRSn field descriptions Field 31 Reserved 30–28 M7 27 Reserved 26–24 M6 23 Reserved 22–20 M5 19 Reserved 18–16 M4 Description This field is reserved. This read-only field is reserved and always has the value 0. Master 7 Priority. Sets the arbitration priority for this port on the associated slave port.
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Chapter 18 Crossbar Switch (AXBS) AXBS_PRSn field descriptions (continued) Field Description 100 101 110 111 15 Reserved 14–12 M3 11 Reserved 10–8 M2 7 Reserved 6–4 M1 3 Reserved 2–0 M0 This master has level 5 priority when accessing the slave port. This master has level 6 priority when accessing the slave port. This master has level 7 priority when accessing the slave port. This master has level 8, or lowest, priority when accessing the slave port. This field is reserved.
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Memory Map / Register Definition AXBS_PRSn field descriptions (continued) Field Description 011 100 101 110 111 This master has level 4 priority when accessing the slave port. This master has level 5 priority when accessing the slave port. This master has level 6 priority when accessing the slave port. This master has level 7 priority when accessing the slave port. This master has level 8, or lowest, priority when accessing the slave port. 18.2.
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Chapter 18 Crossbar Switch (AXBS) AXBS_CRSn field descriptions (continued) Field Description 00 01 10 11 7–6 Reserved 5–4 PCTL This field is reserved. This read-only field is reserved and always has the value 0. Parking Control Determines the slave port’s parking control. The low-power park feature results in an overall power savings if the slave port is not saturated.
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Functional Description 18.2.3 Master General Purpose Control Register (AXBS_MGPCRn) The MGPCR controls only whether the master’s undefined length burst accesses are allowed to complete uninterrupted or whether they can be broken by requests from higher priority masters. The MGPCR can be accessed only in Supervisor mode with 32-bit accesses.
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Chapter 18 Crossbar Switch (AXBS) port, the requesting master simply sees wait states inserted until the targeted slave port can service the master's request. The latency in servicing the request depends on each master's priority level and the responding peripheral's access time. Because the crossbar switch appears to be just another slave to the master device, the master device has no knowledge of whether it actually owns the slave port it is targeting.
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Functional Description The MGPCRx[AULB] bits are the exception to this rule. The update of these bits is only recognized when the master on that master port runs an IDLE cycle, even though the slave bus cycle to write them will have already terminated successfully. If the MGPCRx[AULB] bits are written between two burst accesses, the new AULB encodings do not take effect until an IDLE cycle is initiated by the master on that master port. 18.3.
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Chapter 18 Crossbar Switch (AXBS) continued burst, or the ninth beat of the second burst from the master's perspective, is taken, all beats of the burst are once again open for arbitration until the master loses control of the slave port. Assume the master again loses control of the slave port on the fifth beat of the third now continued burst, or the 10th beat of the second burst from the master's perspective.
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Functional Description Table 18-29. How AXBS grants control of a slave port to a master (continued) When Then AXBS grants control to the requesting master The requesting master's priority level is lower than the current At the conclusion of one of the following cycles: master. • An IDLE cycle • A non-IDLE cycle to a location other than the current slave port 18.3.3.
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Chapter 18 Crossbar Switch (AXBS) 18.4 Initialization/application information No initialization is required by or for the crossbar switch. Hardware reset ensures all the register bits used by the crossbar switch are properly initialized to a valid state. However, settings and priorities may be programmed to achieve maximum system performance. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Initialization/application information K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 362 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 19 Peripheral Bridge (AIPS-Lite) 19.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The peripheral bridge converts the crossbar switch interface to an interface that can access a majority of peripherals on the device. The peripheral bridge supports up to 128 peripherals . (Not all peripheral slots might be used. See the Chip or Device Configuration chapter and Memory Map chapter for details on slot assignment.
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Memory map/register definition 19.1.2 General operation The peripherals connected to the peripheral bridge are modules that contain readable/ writable control and status registers. The system masters read and write these registers through the peripheral bridge.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPS memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_0000 Master Privilege Register A (AIPS0_MPRA) 32 R/W Undefined 19.2.1/366 4000_0020 Peripheral Access Control Register (AIPS0_PACRA) 32 R/W 4444_4444h 19.2.2/368 4000_0024 Peripheral Access Control Register (AIPS0_PACRB) 32 R/W 4444_4444h 19.2.2/368 4000_0028 Peripheral Access Control Register (AIPS0_PACRC) 32 R/W 4444_4444h 19.2.
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Memory map/register definition 19.2.1 Master Privilege Register A (AIPSx_MPRA) The MPRA specifies identical 4-bit fields defining the access-privilege level associated with a bus master in the device to various peripherals. The register provides one field per bus master. NOTE At reset, the default value loaded into the MPRA fields is device-specific. See the chip configuration details for the value of a particular device.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_MPRA field descriptions (continued) Field Description 0 1 29 MTW0 Master Trusted For Writes Determines whether the master is trusted for write accesses. 0 1 28 MPL0 26 MTR1 Specifies how the privilege level of the master is determined. Master trusted for read Determines whether the master is trusted for read accesses. Determines whether the master is trusted for write accesses. 22 MTR2 Specifies how the privilege level of the master is determined.
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Memory map/register definition AIPSx_MPRA field descriptions (continued) Field Description 0 1 19 Reserved 18 MTR3 This field is reserved. This read-only field is reserved and always has the value 0. Master Trusted For Read Determines whether the master is trusted for read accesses. 0 1 17 MTW3 This master is not trusted for read accesses. This master is trusted for read accesses. Master Trusted For Writes Determines whether the master is trusted for write accesses.
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Chapter 19 Peripheral Bridge (AIPS-Lite) The following table shows the top-level structure of PACRs.
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Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description 0 1 29 WP0 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 1 28 TP0 26 SP1 Determines whether the peripheral allows accesses from an untrusted master.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description 0 1 21 WP2 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 1 20 TP2 18 SP3 Determines whether the peripheral allows accesses from an untrusted master.
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Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description 0 1 13 WP4 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 1 12 TP4 10 SP5 Determines whether the peripheral allows accesses from an untrusted master.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description 0 1 5 WP6 Write Protect Determines whether the peripheral allows write accessses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates . 0 1 4 TP6 2 SP7 Determines whether the peripheral allows accesses from an untrusted master.
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Memory map/register definition • PACRA- P define the access levels for the 128 peripherals The peripheral assignments to each PACR are defined by the memory map slot that the peripherals are assigned. See the device's memory map details for the assignments for a particular device. NOTE The reset value of the PACRE- P depends on the device's configuration.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description 0 1 27 Reserved 26 SP1 This field is reserved. This read-only field is reserved and always has the value 0. Supervisor Protect Determines whether the peripheral requires supervisor privilege level for access. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set.
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Memory map/register definition AIPSx_PACRn field descriptions (continued) Field Description 0 1 19 Reserved 18 SP3 This field is reserved. This read-only field is reserved and always has the value 0. Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set.
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Chapter 19 Peripheral Bridge (AIPS-Lite) AIPSx_PACRn field descriptions (continued) Field Description 0 1 11 Reserved 10 SP5 This field is reserved. This read-only field is reserved and always has the value 0. Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set.
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Functional description AIPSx_PACRn field descriptions (continued) Field Description 0 1 3 Reserved 2 SP7 This field is reserved. This read-only field is reserved and always has the value 0. Supervisor Protect Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field for the master must be set.
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Chapter 19 Peripheral Bridge (AIPS-Lite) All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted which is larger than the targeted port, an error response is generated. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Functional description K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 380 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 20.1.1 Overview The direct memory access multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 16 DMA channels. This process is illustrated in the following figure. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Introduction DMAMUX Source #1 DMA Channel #0 DMA Channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA Channel #n Trigger #z Figure 20-1. DMAMUX block diagram 20.1.2 Features The DMA channel MUX provides these features: • 52 peripheral slots and 10 always-on slots can be routed to 16 channels. • 16 independently selectable DMA channel routers. • The first 4 channels additionally provide a trigger functionality.
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger.
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Memory map/register definition DMAMUX memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4002_1009 Channel Configuration register (DMAMUX_CHCFG9) 8 R/W 00h 20.3.1/384 4002_100A Channel Configuration register (DMAMUX_CHCFG10) 8 R/W 00h 20.3.1/384 4002_100B Channel Configuration register (DMAMUX_CHCFG11) 8 R/W 00h 20.3.1/384 4002_100C Channel Configuration register (DMAMUX_CHCFG12) 8 R/W 00h 20.3.
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) DMAMUX_CHCFGn field descriptions (continued) Field Description 0 1 5–0 SOURCE Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic Trigger mode.
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Functional description Source #1 Source #2 Source #3 Trigger #1 Trigger #2 DMA Channel #0 DMA Channel #1 Source #x Always #1 Trigger #4 DMA Channel #3 Always #y Figure 20-19. DMA MUX triggered channels The DMA channel triggering capability allows the system to "schedule" regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen.
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) Peripheral Request Trigger DMA Request Figure 20-21. DMA MUX channel triggering: ignored trigger This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: • Periodically polling external devices on a particular bus. As an example, the transmit side of an SPI is assigned to a DMA channel with a trigger, as described above.
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Initialization/application information • Performing DMA transfers to/from GPIO—Moving data from/to one or more GPIO pins, either unthrottled (that is as fast as possible), or periodically (using the DMA triggering capability). • Performing DMA transfers from memory to memory—Moving data from memory to memory, typically as fast as possible, sometimes with software activation.
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) 20.5.1 Reset The reset state of each individual bit is shown in Memory map/register definition. In summary, after reset, all channels are disabled and must be explicitly enabled before use. 20.5.2 Enabling and configuring sources To enable a source with periodic triggering: 1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability. 2.
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Initialization/application information : *CHCONFIG2 = 0x00; *CHCONFIG2 = 0xC5; To enable a source without periodic triggering: 1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Select the source to be routed to the DMA channel.
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Chapter 20 Direct Memory Access Multiplexer (DMAMUX) 1. Disable the DMA channel in the DMA and re-configure the channel for the new source. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. 3. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] bits are set. To switch DMA channel 8 from source #5 transmit to source #7 transmit: 1.
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Initialization/application information K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 392 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor.
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Introduction eDMA Write Address Write Data 0 Transfer Control Descriptor (TCD) n-1 64 eDMA Engine Program Model/ Channel Arbitration Read Data Read Data Internal Peripheral Bus To/From Crossbar Switch 1 2 Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-1. eDMA block diagram 21.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory.
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Chapter 21 Direct Memory Access Controller (eDMA) Table 21-1. eDMA engine submodules Submodule Address path Function This block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. All the channels provide the same functionality.
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Introduction Table 21-2. Transfer control descriptor memory Submodule Description Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. Memory array TCD storage is implemented using a single-port, synchronous RAM array. 21.1.
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Chapter 21 Direct Memory Access Controller (eDMA) • Channel completion reported via optional interrupt requests • One interrupt per channel, optionally asserted at completion of major iteration count • Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller • Optional support for scatter/gather DMA processing • Support for complex data structures • Support to cancel transfers via software In the discussion of this module, n is used to re
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Memory map/register definition • The first region defines a number of registers providing control functions • The second region corresponds to the local transfer control descriptor memory Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 15 . Each TCDn definition is presented as 11 registers of 16 or 32 bits.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_8034 Hardware Request Status Register (DMA_HRS) 32 R/W 0000_0000h 21.3.15/429 4000_8100 Channel n Priority Register (DMA_DCHPRI3) 8 R/W See section 21.3.16/432 4000_8101 Channel n Priority Register (DMA_DCHPRI2) 8 R/W See section 21.3.16/432 4000_8102 Channel n Priority Register (DMA_DCHPRI1) 8 R/W See section 21.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name 4000_901E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD0_BITER_ELINKNO) 16 4000_9020 TCD Source Address (DMA_TCD1_SADDR) 4000_9024 TCD Signed Source Address Offset (DMA_TCD1_SOFF) 4000_9026 Width Access (in bits) Reset value Section/ page R/W Undefined 21.3.31/445 32 R/W Undefined 21.3.17/433 16 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9056 DMA_TCD2_CITER_ELINKNO 16 R/W Undefined 21.3.27/440 4000_9058 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD2_DLASTSGA) 32 R/W Undefined 21.3.28/441 4000_905C TCD Control and Status (DMA_TCD2_CSR) 16 R/W Undefined 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_908C TCD Last Source Address Adjustment (DMA_TCD4_SLAST) 32 R/W Undefined 21.3.23/438 4000_9090 TCD Destination Address (DMA_TCD4_DADDR) 32 R/W Undefined 21.3.24/438 4000_9094 TCD Signed Destination Address Offset (DMA_TCD4_DOFF) 16 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_90C6 TCD Transfer Attributes (DMA_TCD6_ATTR) 16 R/W Undefined 21.3.19/434 4000_90C8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD6_NBYTES_MLNO) 32 R/W Undefined 21.3.20/435 4000_90C8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD6_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_90FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD7_BITER_ELINKYES) 16 R/W Undefined 21.3.30/444 4000_90FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD7_BITER_ELINKNO) 16 R/W Undefined 21.3.31/445 4000_9100 TCD Source Address (DMA_TCD8_SADDR) 32 R/W Undefined 21.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9134 TCD Signed Destination Address Offset (DMA_TCD9_DOFF) 16 R/W Undefined 21.3.25/439 4000_9136 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD9_CITER_ELINKYES) 16 R/W Undefined 21.3.26/439 4000_9136 DMA_TCD9_CITER_ELINKNO 16 R/W Undefined 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9168 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD11_NBYTES_MLNO) 32 R/W Undefined 21.3.20/435 4000_9168 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD11_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_919E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD12_BITER_ELINKYES) 16 R/W Undefined 21.3.30/444 4000_919E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD12_BITER_ELINKNO) 16 R/W Undefined 21.3.
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Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_91D0 TCD Destination Address (DMA_TCD14_DADDR) 32 R/W Undefined 21.3.24/438 4000_91D4 TCD Signed Destination Address Offset (DMA_TCD14_DOFF) 16 R/W Undefined 21.3.25/439 4000_91D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD14_CITER_ELINKYES) 16 R/W Undefined 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.1 Control Register (DMA_CR) The CR defines the basic operating configuration of the DMA. Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For fixed-priority arbitration, the highest priority channel requesting service is selected to execute. The channel priority registers assign the priorities; see the DCHPRIn registers.
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Memory map/register definition DMA_CR field descriptions (continued) Field Description sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the ES register and generating an optional error interrupt. 15–8 Reserved 7 EMLM This field is reserved. This read-only field is reserved and always has the value 0. Enable Minor Loop Mapping 0 1 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
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Chapter 21 Direct Memory Access Controller (eDMA) • An illegal setting in the transfer-control descriptor, or • An illegal priority register setting in fixed-arbitration • An error termination to a bus master read or write cycle See the Error Reporting and Handling section for more details.
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Memory map/register definition DMA_ES field descriptions (continued) Field Description 6 SOE Source Offset Error 5 DAE Destination Address Error 4 DOE Destination Offset Error 3 NCE NBYTES/CITER Configuration Error 2 SGE Scatter/Gather Configuration Error 1 SBE Source Bus Error 0 DBE Destination Bus Error 0 1 0 1 0 1 0 1 0 1 0 1 0 1 No source offset configuration error The last recorded error was a configuration error detected in the TCDn_SOFF field.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA request input signals and this enable request flag must be asserted before a channel’s hardware service request is accepted. The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request.
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Memory map/register definition DMA_ERQ field descriptions (continued) Field Description 9 ERQ9 Enable DMA Request 9 8 ERQ8 Enable DMA Request 8 7 ERQ7 Enable DMA Request 7 6 ERQ6 Enable DMA Request 6 5 ERQ5 Enable DMA Request 5 4 ERQ4 Enable DMA Request 4 3 ERQ3 Enable DMA Request 3 2 ERQ2 Enable DMA Request 2 1 ERQ1 Enable DMA Request 1 0 ERQ0 Enable DMA Request 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The DMA request signal for the corresponding channel is disabled The DM
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.4 Enable Error Interrupt Register (DMA_ EEI ) The EEI register provides a bit map for the 16 channels to enable the error interrupt signal for each channel. The state of any given channel’s error interrupt enable is directly affected by writes to this register; it is also affected by writes to the SEEI and CEEI.
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Memory map/register definition DMA_EEI field descriptions (continued) Field Description 11 EEI11 Enable Error Interrupt 11 10 EEI10 Enable Error Interrupt 10 9 EEI9 Enable Error Interrupt 9 8 EEI8 Enable Error Interrupt 8 7 EEI7 Enable Error Interrupt 7 6 EEI6 Enable Error Interrupt 6 5 EEI5 Enable Error Interrupt 5 4 EEI4 Enable Error Interrupt 4 3 EEI3 Enable Error Interrupt 3 2 EEI2 Enable Error Interrupt 2 1 EEI1 Enable Error Interrupt 1 0 EEI0 Enable Error Interrupt 0 0 1 0
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI) The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI to disable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs. If the NOP bit is set, the command is ignored.
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Memory map/register definition 21.3.6 Set Enable Error Interrupt Register (DMA_SEEI) The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set function, forcing the entire EEI contents to be set. If the NOP bit is set, the command is ignored.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.7 Clear Enable Request Register (DMA_CERQ) The CERQ provides a simple memory-mapped mechanism to clear a given bit in the ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a global clear function, forcing the entire contents of the ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the command is ignored.
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Memory map/register definition 21.3.8 Set Enable Request Register (DMA_SERQ) The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set function, forcing the entire contents of ERQ to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.9 Clear DONE Status Bit Register (DMA_CDNE) The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting the CADN bit provides a global clear function, forcing all DONE bits to be cleared. If the NOP bit is set, the command is ignored.
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Memory map/register definition 21.3.10 Set START Bit Register (DMA_SSRT) The SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.11 Clear Error Register (DMA_CERR) The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a global clear function, forcing the ERR contents to be cleared, clearing all channel error indicators. If the NOP bit is set, the command is ignored.
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Memory map/register definition 21.3.12 Clear Interrupt Request Register (DMA_CINT) The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a global clear function, forcing the entire contents of the INT to be cleared, disabling all DMA interrupt requests. If the NOP bit is set, the command is ignored.
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Chapter 21 Direct Memory Access Controller (eDMA) The state of any given channel’s interrupt request is directly affected by writes to this register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit position clears the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding channel’s current interrupt status.
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Memory map/register definition DMA_INT field descriptions (continued) Field Description 11 INT11 Interrupt Request 11 10 INT10 Interrupt Request 10 9 INT9 Interrupt Request 9 8 INT8 Interrupt Request 8 7 INT7 Interrupt Request 7 6 INT6 Interrupt Request 6 5 INT5 Interrupt Request 5 4 INT4 Interrupt Request 4 3 INT3 Interrupt Request 3 2 INT2 Interrupt Request 2 1 INT1 Interrupt Request 1 0 INT0 Interrupt Request 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The int
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.14 Error Register (DMA_ ERR ) The ERR provides a bit map for the 16 channels, signaling the presence of an error for each channel. The eDMA engine signals the occurrence of an error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the contents of the EEI, and then routed to the interrupt controller.
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Memory map/register definition DMA_ERR field descriptions Field 31–16 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_ERR field descriptions (continued) Field Description 0 1 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred 3 ERR3 Error In Channel 3 2 ERR2 Error In Channel 2 1 ERR1 Error In Channel 1 0 ERR0 Error In Channel 0 0 1 0 1 0 1 0 1 An error in the corresponding channel has not occurred An error in the corresponding channel has occurred An error in the corresponding channel has not occurr
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15 14 13 12 11 10 W HRS15 HRS14 HRS13 HRS12 HRS11 HRS10 Memory map/register definition Reset 0 0 0 0 0 0 Bit R 9 8 7 6 5 4 3 2 1 0 HRS9 HRS8 HRS7 HRS6 HRS5 HRS4 HRS3 HRS2 HRS1 HRS0 0 0 0 0 0 0 0 0 0 0 DMA_HRS field descriptions Field 31–16 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_HRS field descriptions (continued) Field Description 0 1 A hardware service request for the corresponding channel is not present A hardware service request for the corresponding channel is present 5 HRS5 Hardware Request Status Channel 5 4 HRS4 Hardware Request Status Channel 4 3 HRS3 Hardware Request Status Channel 3 2 HRS2 Hardware Request Status Channel 2 1 HRS1 Hardware Request Status Channel 1 0 HRS0 Hardware Request Status Channel 0
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Memory map/register definition 21.3.16 Channel n Priority Register (DMA_DCHPRIn) When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel . The channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next priority, then 2, 3, etc. Software must program the channel priorities with unique values. Otherwise, a configuration error is reported.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.17 TCD Source Address (DMA_TCDn_SADDR) Address: 4000_8000h base + 1000h offset + (32d × i), where i=0d to 15d Bit R W Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SADDR x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: • x = Undefined at reset.
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Memory map/register definition 21.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR) Address: 4000_8000h base + 1006h offset + (32d × i), where i=0d to 15d Bit Read Write Reset 15 14 13 12 11 10 SMOD x* x* x* 9 8 7 6 SSIZE x* x* x* x* 5 4 3 2 DMOD x* x* x* x* 1 0 DSIZE x* x* x* x* x* * Notes: • x = Undefined at reset. DMA_TCDn_ATTR field descriptions Field Description 15–11 SMOD Source Address Modulo.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO) TCD word 2's register definition depends on the status of minor loop mapping. If minor loop mapping is disabled (CR[EMLM] = 0), TCD word 2 is defined as follows. If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions for TCD word 2's register definition.
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Memory map/register definition 31 30 W SMLOE DMLOE Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d Bit Reset x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 R 29 28 27 26 25 24 23 22 21 20 19 18 17 16 x* x* x* x* x* x* x* 6 5 4 3 2 1 0 x* x* x* x* x* x* x* NBYTES R NBYTES W Reset x* x* x* x* x* x* x* x* x* * Notes: • x = Undefined at reset.
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Chapter 21 Direct Memory Access Controller (eDMA) If minor loop mapping is enabled and SMLOE and DMLOE are cleared then refer to the TCD_NBYTES_MLOFFNO register description.
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Memory map/register definition 21.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST) Address: 4000_8000h base + 100Ch offset + (32d × i), where i=0d to 15d Bit R W Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLAST x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: • x = Undefined at reset.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF) Address: 4000_8000h base + 1014h offset + (32d × i), where i=0d to 15d Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x* x* x* x* x* x* x* x* DOFF x* x* x* x* x* x* x* x* * Notes: • x = Undefined at reset.
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Memory map/register definition DMA_TCDn_CITER_ELINKYES field descriptions (continued) Field Description If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: This bit must be equal to the BITER[ELINK] bit. Otherwise, a configuration error is reported.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_CITER_ELINKNO field descriptions Field Description 15 ELINK Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.
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Memory map/register definition DMA_TCDn_DLASTSGA field descriptions (continued) Field Description else • This address points to the beginning of a 0-modulo-32-byte region containing the next transfer control descriptor to be loaded into this channel. This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, else a configuration error is reported. 21.3.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_CSR field descriptions (continued) Field Description • After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by these six bits by setting that channel’s TCDn_CSR[START] bit. 7 DONE Channel Done This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count reaches zero; The software clears it, or the hardware when the channel is activated.
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Memory map/register definition DMA_TCDn_CSR field descriptions (continued) Field 1 INTMAJOR Description Enable an interrupt when major iteration count completes If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero. 0 1 0 START The end-of-major loop interrupt is disabled The end-of-major loop interrupt is enabled Channel Start If this flag is set, the channel is requesting service.
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Chapter 21 Direct Memory Access Controller (eDMA) DMA_TCDn_BITER_ELINKYES field descriptions (continued) Field Description 0 1 14–13 Reserved 12–9 LINKCH The channel-to-channel linking is disabled The channel-to-channel linking is enabled This field is reserved. This read-only field is reserved and always has the value 0.
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Functional description DMA_TCDn_BITER_ELINKNO field descriptions (continued) Field Description As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the BITER value extends to 15 bits in place of a link channel number.
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Chapter 21 Direct Memory Access Controller (eDMA) eDMA Write Address Write Data 0 Transfer Control Descriptor (TCD) 64 eDMA Engine Program Model/ Channel Arbitration Read Data n-1 Internal Peripheral Bus To/From Crossbar Switch 1 2 Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-289. eDMA operation, part 1 This example uses the assertion of the eDMA peripheral request signal to request service for channel n.
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Functional description eDMA Write Address Write Data To/From Crossbar Switch Transfer Control Descriptor (TCD) n-1 64 eDMA Engine Program Model/ Channel Arbitration Read Data Internal Peripheral Bus 0 1 2 Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-290.
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Chapter 21 Direct Memory Access Controller (eDMA) eDMA Write Address Write Data To/From Crossbar Switch Transfer Control Descriptor (TCD) n-1 64 Internal Peripheral Bus 0 1 2 eDMA En g in e Program Model/ Channel Arbitration Read Data Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 21-291. eDMA operation, part 3 21.4.
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Functional description • All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. • In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal. All channel priority levels must be unique when fixed arbitration mode is enabled.
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Chapter 21 Direct Memory Access Controller (eDMA) The occurrence of any error causes the eDMA engine to stop normal processing of the active channel immediately (it goes to its error processing states and the transaction to the system bus still has peipeline effect), and the appropriate channel bit in the eDMA error register is asserted. At the same time, the details of the error condition are loaded into the ES register.
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Functional description • In the traditional data movement context, performance is best expressed as the peak data transfer rates achieved using the eDMA. In most implementations, this transfer rate is limited by the speed of the source and destination address spaces. • In a second context where device-paced movement of single data values to/from peripherals is dominant, a measure of the requests that can be serviced in a fixed time is a more relevant metric.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.4.4.2 Peak request rates The second performance metric is a measure of the number of DMA requests that can be serviced in a given amount of time. For this metric, assume that the peripheral request causes the channel to move a single internal peripheral bus-mapped operand to/from internal SRAM. The same timing assumptions used in the previous example apply to this calculation.
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Functional description Table 21-293. Hardware service request process (continued) Cycle Description With internal peripheral bus read and internal SRAM write With SRAM read and internal peripheral bus write 15 16 The fields in the second part of the TCDn are written back into the local memory. This cycle coincides with the next channel arbitration cycle start. 16 17 The next channel to be activated performs the read of the first part of its TCD from the local memory.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.4.4.
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Initialization/application information 21.5 Initialization/application information The following sections discuss initialization of the eDMA and programming considerations. 21.5.1 eDMA initialization To initialize the eDMA: 1. Write to the CR if a configuration other than the default is desired. 2. Write the channel priority levels to the DCHPRIn registers if a configuration other than the default is desired. 3. Enable error interrupts in the EEI register if so desired. 4.
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Chapter 21 Direct Memory Access Controller (eDMA) Table 21-296.
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Initialization/application information xADDR: (Starting address) xSIZE: (size of one data transfer) Minor loop (NBYTES in minor loop, often the same value as xSIZE) Minor loop Offset (xOFF): number of bytes added to current address after each transfer (often the same value as xSIZE) Each DMA source (S) and destination (D) has its own: Address (xADDR) Size (xSIZE) Offset (xOFF) Modulo (xMOD) Last Address Adjustment (xLAST) where x = S or D Last minor loop Peripheral queues typically have size and offse
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Chapter 21 Direct Memory Access Controller (eDMA) 21.5.3.2 Round-robin channel arbitration Channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels. 21.5.4 Performing DMA transfers (examples) 21.5.4.1 Single request To perform a simple transfer of n bytes of data with one activation, set the major loop to one (TCDn_CITER = TCDn_BITER = 1).
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Initialization/application information 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source-to-destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. Write 32-bits to location 0x2000 → first iteration of the minor loop. c. Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d.
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Chapter 21 Direct Memory Access Controller (eDMA) 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. 4. eDMA engine reads: channel TCDn data from local memory to internal register file. 5. The source to destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b.
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Initialization/application information b. Write 32-bits to location 0x2010 → first iteration of the minor loop. c. Read byte from location 0x1014, read byte from location 0x1015, read byte from 0x1016, read byte from 0x1017. d. Write 32-bits to location 0x2014 → second iteration of the minor loop. e. Read byte from location 0x1018, read byte from location 0x1019, read byte from 0x101A, read byte from 0x101B. f. Write 32-bits to location 0x2018 → third iteration of the minor loop. g.
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Chapter 21 Direct Memory Access Controller (eDMA) Table 21-297. Modulo example (continued) Transfer Number Address 2 0x12345674 3 0x12345678 4 0x1234567C 5 0x12345670 6 0x12345674 21.5.5 Monitoring transfer descriptor status 21.5.5.1 Testing for minor loop completion There are two methods to test for minor loop completion when using software initiated service requests. The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below.
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Initialization/application information Stage TCDn_CSR bits State START ACTIVE DONE 1 0 0 0 Channel service request via hardware (peripheral request asserted) 2 0 1 0 Channel is executing 3a 0 0 0 Channel has completed the minor loop and is idle 3b 0 0 1 Channel has completed the major loop and is idle For both activation types, the major-loop-complete status is explicitly indicated via the TCDn_CSR[DONE] bit.
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Chapter 21 Direct Memory Access Controller (eDMA) 21.5.6 Channel Linking Channel linking (or chaining) is a mechanism where one channel sets the TCDn_CSR[START] bit of another channel (or itself), therefore initiating a service request for that channel. When properly enabled, the EDMA engine automatically performs this operation at the major or minor loop completion. The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major loop).
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Initialization/application information Table 21-298.
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Chapter 21 Direct Memory Access Controller (eDMA) Step Action 1 Write 1b to the TCD.major.e_link bit. 2 Read back the TCD.major.e_link bit. 3 Test the TCD.major.e_link request status: • If TCD.major.e_link = 1b, the dynamic link attempt was successful. • If TCD.major.e_link = 0b, the attempted dynamic link did not succeed (the channel was already retiring). For this request, the TCD local memory controller forces the TCD.major.e_link bit to zero on any writes to a channel’s TCD.
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Initialization/application information cleared automatically by the eDMA engine after a channel begins execution. 21.5.7.3.1 Method 1 (channel not using major loop channel linking) For a channel not using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request. When the TCD.major.e_link bit is zero, the TCD.major.linkch field is not used by the eDMA. In this case, the TCD.major.linkch bits may be used for other purposes. This method uses the TCD.
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Chapter 21 Direct Memory Access Controller (eDMA) For a channel using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request. This method uses the TCD.dlast_sga field as a TCD indentification (ID). 1. Write 1b to the TCD.d_req bit. Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future hardware activation of this channel.
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Initialization/application information K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 470 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 22 External Watchdog Monitor (EWM) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The watchdog is generally used to monitor the flow and execution of embedded software within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET pin to reset external devices/circuits.
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Introduction • Windowed refresh option • Provides robust check that program flow is faster than expected. • Programmable window. • Refresh outside window leads to assertion of EWM_out. • Robust refresh mechanism • Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 (EWM_service_time) peripheral bus clock cycles. • One output port, EWM_out, when asserted is used to reset or place the external circuit into safe mode.
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Chapter 22 External Watchdog Monitor (EWM) 22.1.2.2 Wait Mode The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. 22.1.2.3 Debug Mode Entry to debug mode has no effect on the EWM. • If the EWM is enabled prior to entry of debug mode, it remains enabled. • If the EWM is disabled prior to entry of debug mode, it remains disabled. 22.1.3 Block Diagram This figure shows the EWM block diagram.
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EWM Signal Descriptions 22.2 EWM Signal Descriptions The EWM has two external signals, as shown in the following table. Table 22-1. EWM Signal Descriptions Signal Description EWM_in EWM_out I/O EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. I EWM reset out signal O 22.3 Memory Map/Register Definition This section contains the module memory map and registers.
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Chapter 22 External Watchdog Monitor (EWM) EWM_CTRL field descriptions Field 7–4 Reserved 3 INTEN 2 INEN 1 ASSIN 0 EWMEN Description This field is reserved. This read-only field is reserved and always has the value 0. Interrupt Enable. This bit when set and EWM_out is asserted, an interrupt request is generated. To de-assert interrupt request, user should clear this bit by writing 0. Input Enable. This bit when set, enables the EWM_in port. EWM_in's Assertion State Select.
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Memory Map/Register Definition NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error.
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Chapter 22 External Watchdog Monitor (EWM) 22.4 Functional Description The following sections describe functional details of the EWM module. 22.4.1 The EWM_out Signal The EWM_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. For example, the EWM_out could be connected to the high voltage transistors circuits that control an AC motor in a large appliance.
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Functional Description 22.4.2 The EWM_in Signal The EWM_in is a digital input signal that allows an external circuit to control the EWM_out signal. For example, in the application, an external circuit monitors a critical safety function, and if there is fault with this circuit's behavior, it can then actively initiate the EWM_out signal that controls the gating circuit. The EWM_in signal is ignored if the EWM is disabled, or if INEN bit of CTRL register is cleared, as after any reset.
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Chapter 22 External Watchdog Monitor (EWM) • If the CPU services the EWM when the counter value lies between CMPL value and CMPH value, the counter is reset to zero. This is a legal service operation. • If the CPU executes a EWM service/refresh action outside the legal service window, EWM_out is asserted. It is illegal to program CMPL and CMPH with same value. In this case, as soon as counter reaches (CMPL + 1), EWM_out is asserted. 22.4.
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Functional Description K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 480 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 23 Watchdog Timer (WDOG) 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. Reasons for failure include run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences. In such cases, the watchdog brings the system into a safe state of operation.
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Features • You need to always update these bits after unlocking within 256 bus clock cycles. Failure to update these bits resets the system. • Programmable time-out period specified in terms of number of WDOG clock cycles. • Ability to test WDOG timer and reset with a flag indicating watchdog test. • Quick test—Small time-out value programmed for quick test. • Byte test—Individual bytes of timer tested one at a time. • Read-only access to the WDOG timer—Allows dynamic check that WDOG timer is operational.
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Chapter 23 Watchdog Timer (WDOG) 23.
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Functional overview to be serviced periodically, failing which it resets the system. This ensures that the software is executing correctly and has not run away in an unintended direction. Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application. You can select a windowed mode of operation that expects the servicing to be done only in a particular window of the time-out period.
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Chapter 23 Watchdog Timer (WDOG) The update feature is useful for applications that have an initial, non-safety critical part, where the watchdog is kept disabled or with a conveniently long time-out period. This means the application coder does not have to frequently service the watchdog. After the critical part of the application begins, the watchdog can be reconfigured as needed.
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Functional overview Updates in the write-once registers take effect only after the WCT window closes with the following exceptions for which changes take effect immediately: • Stop, Wait, and Debug mode enable • IRQ_RST_EN The operations of refreshing the watchdog goes undetected during the WCT. 23.3.3 Refreshing the watchdog A robust refreshing mechanism has been chosen for the watchdog. A valid refresh is a write of 0xA602 followed by 0xB480 within 20 bus clock cycles to watchdog refresh register.
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Chapter 23 Watchdog Timer (WDOG) time-out exception. See Generated Resets and Interrupts. You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode. 23.3.6 Low-power modes of operation The low-power modes of operation of the watchdog are described in the following table: Table 23-1.
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Testing the watchdog 23.4 Testing the watchdog For IEC 60730 and other safety standards, the expectation is that anything that monitors a safety function must be tested, and this test is required to be fault tolerant. To test the watchdog, its main timer and its associated compare and reset logic must be tested. To this end, two tests are implemented for the watchdog, as described in Quick Test and Byte Test. A control bit is provided to put the watchdog into functional test mode.
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Chapter 23 Watchdog Timer (WDOG) 23.4.1 Quick test In this test, the time-out value of watchdog timer is programmed to a very low value to achieve quick time-out. The only difference between the quick test and the normal mode of the watchdog is that TESTWDOG is set for the quick test. This allows for a faster test of the watchdog reset mechanism. 23.4.2 Byte test The byte test is a more thorough a test of the watchdog timer.
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Backup reset generator other stages, N – 2, N – 3... and N + 1, N + 2... are enabled for the test on byte N. These disabled stages, except the most significant stage of the counter, are loaded with a value of 0xFF. 23.5 Backup reset generator The backup reset generator generates the final reset which goes out to the system.
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Chapter 23 Watchdog Timer (WDOG) The watchdog can also generate an interrupt. If IRQ_RST_EN is set, then on the above mentioned events WDOG_ST_CTRL_L[INT_FLG] is set, generating an interrupt. A watchdog reset is also generated WCT time later to ensure the watchdog is fault tolerant. The interrupt can be cleared by writing 1 to INT_FLG. The gap of WCT between interrupt and reset means that the WDOG time-out value must be greater than WCT.
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Memory map and register definition 23.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH) 4 3 2 1 0 WDOGEN 0 5 CLKSRC 0 6 IRQRSTEN 0 0 7 WINEN 0 0 8 ALLOWUPDAT E 0 9 DBGEN 0 10 STOPEN Reset 11 WAITEN Write 12 Reserved 0 13 TESTWDOG Read 14 BYTESEL[1:0] 15 DISTESTWDO G Bit TESTSEL Address: 4005_2000h base + 0h offset = 4005_2000h 1 1 1 0 1 0 0 1 1 WDOG_STCTRLH field descriptions Field 15 Reserved Description This field is reserved.
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Chapter 23 Watchdog Timer (WDOG) WDOG_STCTRLH field descriptions (continued) Field Description 0 1 5 DBGEN WDOG is disabled in CPU Stop mode. WDOG is enabled in CPU Stop mode. Enables or disables WDOG in Debug mode. 0 1 WDOG is disabled in CPU Debug mode. WDOG is enabled in CPU Debug mode. 4 Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window ALLOWUPDATE (WCT) closes, through unlock sequence.
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Memory map and register definition WDOG_STCTRLL field descriptions Field Description 15 INTFLG Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a precondition to set this flag. INTFLG = 1 results in an interrupt being issued followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this bit. It also gets cleared on a system reset. 14–0 Reserved This field is reserved. NOTE: Do not modify this field value. 23.7.
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Chapter 23 Watchdog Timer (WDOG) 23.7.5 Watchdog Window Register High (WDOG_WINH) NOTE You must set the Window Register value lower than the Timeout Value Register. Address: 4005_2000h base + 8h offset = 4005_2008h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 WINHIGH 0 0 0 0 0 0 0 0 0 WDOG_WINH field descriptions Field Description 15–0 WINHIGH Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog.
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Memory map and register definition 23.7.7 Watchdog Refresh register (WDOG_REFRESH) Address: 4005_2000h base + Ch offset = 4005_200Ch Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 WDOGREFRESH 1 0 1 1 0 1 0 0 1 WDOG_REFRESH field descriptions Field Description 15–0 Watchdog refresh register.
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Chapter 23 Watchdog Timer (WDOG) WDOG_TMROUTH field descriptions Field Description 15–0 Shows the value of the upper 16 bits of the watchdog timer. TIMEROUTHIGH 23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL) During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following the watchdog timer.
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Watchdog operation with 8-bit access 23.7.12 Watchdog Prescaler register (WDOG_PRESC) Address: 4005_2000h base + 16h offset = 4005_2016h Bit Read Write Reset 15 14 13 12 11 10 0 0 0 0 9 8 7 6 5 4 PRESCVAL 0 0 1 0 3 2 1 0 0 0 0 0 0 0 0 0 0 0 WDOG_PRESC field descriptions Field 15–11 Reserved 10–8 PRESCVAL 7–0 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 3-bit prescaler for the watchdog clock source.
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Chapter 23 Watchdog Timer (WDOG) Whereas the match for a correct value for a refresh/unlock sequence is as according to the original definition, the match for an incorrect value is done byte-wise on the refresh/ unlock rather than for the whole 16-bit value. This means that if the high byte of the refresh/unlock register contains any value other than high bytes of the two values that make up the sequence, it is treated as an exception condition, leading to a reset or interrupt-then-reset.
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Restrictions on watchdog operation • Restriction on unlock/refresh operations—In the period between the closure of the WCT window after unlock and the actual reload of the watchdog timer, unlock and refresh operations need not be attempted. • The update and reload of the watchdog timer happens two to three watchdog clocks after WCT window closes, following a successful configuration on unlock.
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Chapter 23 Watchdog Timer (WDOG) • Trying to unlock the watchdog within the WCT time after an initial unlock has no effect. • The refresh and unlock operations and interrupt are not automatically disabled in the watchdog functional test mode. • After emerging from a reset due to a watchdog functional test, you are still expected to go through the mandatory steps of unlocking and configuring the watchdog.
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Restrictions on watchdog operation K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 502 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL). The FLL is controllable by either an internal or an external reference clock. The PLL is controllable by the external reference clock.
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Introduction • Internal or external reference clock can be used as the FLL source. • Can be used as a clock source for other on-chip peripherals. • Phase-locked loop (PLL): • Voltage-controlled oscillator (VCO) • External reference clock is used as the PLL source. • Modulo VCO frequency divider • Phase/Frequency detector • Integrated loop filter • Can be used as a clock source for other on-chip peripherals.
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Chapter 24 Multipurpose Clock Generator (MCG) • Internal Reference Clocks Auto Trim Machine (ATM) capability using an external clock as a reference • Reference dividers for both the FLL and PLL are provided • Reference dividers for the Fast Internal Reference Clock are provided • MCG PLL Clock (MCGPLLCLK) is provided as a clock source for other on-chip peripherals • MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals • MCG Fixed Frequency Clock (MCGFFCLK) is provided as a
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Introduction RTC Oscillator Crystal Oscillator External Reference Clock CLKS ATMS OSCSEL OSCINIT0 PLLCLKEN0 EREFS0 IREFS HGO0 PLLS RANGE0 MCG Crystal Oscillator Enable Detect STOP IREFSTEN Auto Trim Machine IRCLKEN SCTRIM IRCS Internal Reference SCFTRIM CLKS Slow Clock Clock Generator FCTRIM MCGIRCLK / Fast Clock 2n IRCSCLK n=0-7 MCGOUTCLK MCGFLLCLK CME0 LOCRE0 DRS External Clock Monitor DMX32 Filter DCO FLTPRSRV LOCS0 PLLS DCOOUT FLL FRDIV / IREFS Clock Valid LP
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Chapter 24 Multipurpose Clock Generator (MCG) 24.1.2 Modes of Operation There are nine modes of operation for the MCG: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 24.2 External Signal Description There are no MCG signals that connect off chip. 24.3 Memory Map/Register Definition This section includes the memory map and register definition. The MCG registers can only be written to when in supervisor mode.
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Memory Map/Register Definition 24.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Bit Read Write Reset 7 6 5 CLKS 0 4 3 FRDIV 0 0 0 0 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 MCG_C1 field descriptions Field 7–6 CLKS Description Clock Source Select Selects the clock source for MCGOUTCLK . 00 01 10 11 5–3 FRDIV FLL External Reference Divider Selects the amount to divide down the external reference clock for the FLL.
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Chapter 24 Multipurpose Clock Generator (MCG) MCG_C1 field descriptions (continued) Field Description 0 1 0 IREFSTEN MCGIRCLK inactive. MCGIRCLK active. Internal Reference Stop Enable Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. 0 1 Internal reference clock is disabled in Stop mode. Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. 24.3.
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Memory Map/Register Definition MCG_C2 field descriptions (continued) Field Description 0 1 1 LP External reference clock requested. Oscillator requested. Low Power Select Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any other MCG mode, LP bit has no affect. 0 1 0 IRCS FLL or PLL is not disabled in bypass modes.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.3.4 MCG Control 4 Register (MCG_C4) NOTE Reset values for DRST and DMX32 bits are 0. Address: 4006_4000h base + 3h offset = 4006_4003h Bit Read Write Reset 7 6 DMX32 5 4 3 DRST_DRS 0 0 2 1 FCTRIM 0 x* x* 0 SCFTRIM x* x* x* * Notes: • x = Undefined at reset. • A value for FCTRIM is loaded during reset from a factory programmed location . x = Undefined at reset.
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Memory Map/Register Definition MCG_C4 field descriptions (continued) Field Description 01 10 11 4–1 FCTRIM Encoding 1 — Mid range. Encoding 2 — Mid-high range. Encoding 3 — High range. Fast Internal Reference Clock Trim Setting FCTRIM 1 controls the fast internal reference clock frequency by controlling the fast internal reference clock period. The FCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0.
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Chapter 24 Multipurpose Clock Generator (MCG) MCG_C5 field descriptions (continued) Field Description Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit has no affect and does not enable the PLL Clock to run if it is written to 1. 0 1 4–0 PRDIV0 MCGPLLCLK is disabled in any of the Stop modes. MCGPLLCLK is enabled if system is in Normal Stop mode.
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Memory Map/Register Definition MCG_C6 field descriptions (continued) Field Description Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect when LOLS 0 is set. 0 1 6 PLLS PLL Select Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is disabled in all modes. If the PLLS is set, the FLL is disabled in all modes. 0 1 5 CME0 FLL is selected.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.3.7 MCG Status Register (MCG_S) Address: 4006_4000h base + 6h offset = 4006_4006h Bit Read 7 6 5 4 LOLS0 LOCK0 PLLST IREFST 3 0 0 0 1 2 CLKST 1 0 OSCINIT0 IRCST 0 0 Write Reset 0 0 MCG_S field descriptions Field 7 LOLS0 Description Loss of Lock Status This bit is a sticky bit indicating the lock status for the PLL.
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Memory Map/Register Definition MCG_S field descriptions (continued) Field 3–2 CLKST Description Clock Mode Status These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 01 10 11 1 OSCINIT0 0 IRCST Encoding 0 — Output of the FLL is selected (reset default). Encoding 1 — Internal reference clock is selected. Encoding 2 — External reference clock is selected.
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Chapter 24 Multipurpose Clock Generator (MCG) MCG_SC field descriptions (continued) Field 6 ATMS Description Automatic Trim Machine Select Selects the IRCS clock for Auto Trim Test. 0 1 5 ATMF Automatic Trim Machine Fail Flag Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC registers is detected or the MCG enters into any Stop mode. A write to ATMF clears the flag.
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Memory Map/Register Definition 24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH) Address: 4006_4000h base + Ah offset = 4006_400Ah Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 ATCVH 0 0 0 0 MCG_ATCVH field descriptions Field 7–0 ATCVH Description ATM Compare Value High Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 24.3.
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Chapter 24 Multipurpose Clock Generator (MCG) MCG_C7 field descriptions Field Description 7–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 OSCSEL MCG OSC Clock Select Selects the MCG FLL external reference clock 0 1 Selects System Oscillator (OSCCLK). Selects 32 kHz RTC Oscillator. 24.3.
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Functional description MCG_C8 field descriptions (continued) Field Description 0 1 Loss of RTC has not occur. Loss of RTC has occur 24.4 Functional description 24.4.1 MCG mode state diagram The nine states of the MCG are shown in the following figure and are described in Table 24-16. The arrows indicate the permitted MCG mode transitions.
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Chapter 24 Multipurpose Clock Generator (MCG) NOTE • During exits from LLS or VLPS when the MCG is in PEE mode, the MCG will reset to PBE clock mode and the C1[CLKS] and S[CLKST] will automatically be set to 2’b10. • If entering Normal Stop mode when the MCG is in PEE mode with C5[PLLSTEN]=0, the MCG will reset to PBE clock mode and C1[CLKS] and S[CLKST] will automatically be set to 2’b10. 24.4.1.1 MCG modes of operation The MCG operates in one of the following modes.
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Functional description Table 24-16. MCG modes of operation (continued) Mode Description FLL Engaged External (FEE) FLL engaged external (FEE) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 0 • C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.
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Chapter 24 Multipurpose Clock Generator (MCG) Table 24-16. MCG modes of operation (continued) Mode Description PLL Engaged External (PEE) PLL Engaged External (PEE) mode is entered when all the following conditions occur: • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 0 • C6[PLLS] bit is written to 1 In PEE mode, the MCGOUTCLK is derived from the PLL clock, which is controlled by the external reference clock.
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Functional description Table 24-16. MCG modes of operation (continued) Mode Description Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power mode assignments, see the chapter that describes how modules are configured and MCG behavior during Stop recovery.
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Chapter 24 Multipurpose Clock Generator (MCG) the FLL remains unlocked for several reference cycles. DCO startup time is equal to the FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the C4[DRST_DRS] read bits. 24.4.2 Low Power Bit Usage The C2[LP] bit is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used. The C4[DRST_DRS] can not be written while C2[LP] bit is 1.
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Functional description 24.4.4 External Reference Clock The MCG module can support an external reference clock in all modes. See the device datasheet for external reference frequency range. When C1[IREFS] is set, the external reference clock will not be used by the FLL or PLL. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.4.7 MCG Auto TRIM (ATM) The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference. The selection between which MCG IRC clock gets tested and enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz IRC and ATC[ATMS]=1 selects the 4 MHz IRC).
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Initialization / Application information If the auto trim is being performed on the 4 MHz IRC, the calculated expected count value must be multiplied by 128 before storing it in the ATCV register. Therefore, the ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following formula. (128) 24.5 Initialization / Application information This section describes how to initialize and configure the MCG module in an application.
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Chapter 24 Multipurpose Clock Generator (MCG) appropriately here according to the external reference frequency to keep the FLL reference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL is bypassed, it is still on in FBE mode. • The internal reference can optionally be kept running by setting the C1[IRCLKEN] bit. This is useful if the application will switch back and forth between internal and external modes.
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Initialization / Application information • When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48 MHz. • When using a 32.768 kHz external reference, if the maximum mid high-range DCO frequency that can be achieved with a 32.
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Chapter 24 Multipurpose Clock Generator (MCG) resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output frequency is 83.89 MHz at high-range. In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal reference is trimmed to a frequency above 32.
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Initialization / Application information Table 24-17. MCGOUTCLK Frequency Calculation Options (continued) Clock Mode fMCGOUTCLK1 Note PBE (PLL bypassed external) fext fext / PLL_R must be in the range specified for fpll_ref in the appropriate device Data Sheet BLPI (Bypassed low power internal) fint BLPE (Bypassed low power external) fext 1.
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Chapter 24 Multipurpose Clock Generator (MCG) c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by C2[EREFS0] has been initialized. d. Loop until S[IREFST] is 0, indicating the external reference is the current source for the reference clock. e. Loop until S[CLKST] is 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK. 2. Then configure C5[PRDIV0] to generate correct PLL reference frequency. a.
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Initialization / Application information • C1[CLKS] set to 2'b00 to select the output of the PLL as the system clock source. b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode. • Now, with PRDIV0 of divide-by-2, and C6[VDIV0] of multiply-by-24, MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 534 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 24 Multipurpose Clock Generator (MCG) START IN FEI MODE C6 = 0x40 C2 = 0x1C IN BLPE MODE ? (S[LP]=1) C1 = 0x90 NO YES C2 = 0x1C (S[LP]=0) NO CHECK S[OSCINIT] = 1? CHECK S[PLLST] = 1? YES CHECK S[IREFST] = 0? NO YES NO CHECK S[LOCK] = 1? YES CHECK NO S[CLKST] = %10? NO YES C1 = 0x10 YES C5 = 0x01 (C5[VDIV] = 1) ENTER BLPE MODE ? CHECK S[CLKST] = %11? NO YES NO CONTINUE YES IN PEE MODE C2 = 0x1E (C2[LP] = 1) Figure 24-15.
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Initialization / Application information 24.5.3.2 Example 2: Moving from PEE to BLPI mode: MCGOUTCLK frequency =32 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, PEE must transition to PBE mode: a.
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Chapter 24 Multipurpose Clock Generator (MCG) • C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. • C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source. c. Loop until S[CLKST] are 2'b01, indicating that the internal reference clock is selected to feed MCGOUTCLK. 4. Lastly, FBI transitions into BLPI mode. a.
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Initialization / Application information START IN PEE MODE C1 = 0x90 CHECK S[PLLST] = 0? NO CHECK S[CLKST] = %10 ? YES C1 = 0x54 YES ENTER NO NO CHECK S[IREFST] = 0? BLPE MODE ? YES NO YES C2 = 0x1E (C2[LP] = 1) CHECK S[CLKST] = %01? NO C6 = 0x00 YES C2 = 0x02 IN BLPE MODE ? (C2[LP]=1) NO CONTINUE YES IN BLPI MODE C2 = 0x1C (C2[LP] = 0) Figure 24-16. Flowchart of PEE to BLPI mode transition using an 4 MHz crystal K20 Sub-Family Reference Manual, Rev. 1.
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Chapter 24 Multipurpose Clock Generator (MCG) 24.5.3.3 Example 3: Moving from BLPI to FEE mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, BLPI must transition to FBI mode. a.
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Initialization / Application information multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. START IN BLPI MODE CHECK NO S[IREFST] = 0? C2 =0x00 YES C2 = 0x1C NO CHECK S[CLKST] = %00? C1 =0x10 YES CONTINUE CHECK S[OSCINIT] = 1 ? NO IN FEE MODE YES Figure 24-17. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal K20 Sub-Family Reference Manual, Rev. 1.
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Chapter 25 Oscillator (OSC) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 25.
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Block Diagram 25.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals. Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode. OSCERCLK and OSC32KCLK can work in low power modes. For the clock source assignments, refer to the clock distribution information of this MCU.
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Chapter 25 Oscillator (OSC) Table 25-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input I Oscillator output O XTAL I/O 25.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the following figures. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself.
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External Clock Connections OSC XTAL EXTAL VSS RF Crystal or Resonator Figure 25-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. OSC XTAL EXTAL VSS Cx Cy RF Crystal or Resonator Figure 25-4. Crystal/Ceramic Resonator Connections - Connection 3 25.6 External Clock Connections In external clock mode, the pins can be connected as shown below.
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Chapter 25 Oscillator (OSC) OSC XTAL EXTAL VSS Clock Input I/O Figure 25-5. External Clock Connections 25.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 25.7.1 OSC Memory Map/Register Definition OSC memory map Absolute address (hex) 4006_5000 Width Access (in bits) Register name OSC Control Register (OSC_CR) 8 R/W Reset value Section/ page 00h 25.71.1/ 545 25.71.
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Functional Description OSC_CR field descriptions Field 7 ERCLKEN Description External Reference Enable Enables external reference clock (OSCERCLK). 0 1 6 Reserved 5 EREFSTEN This field is reserved. This read-only field is reserved and always has the value 0. External Reference Stop Enable Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. 0 1 4 Reserved 3 SC2P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load.
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Chapter 25 Oscillator (OSC) 25.8.1 OSC Module States The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section.
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Functional Description 25.8.1.2 Oscillator Start-Up The OSC enters start-up state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized. When the oscillation amplitude becomes large enough to pass through the input buffer, XTL_CLK begins clocking the counter.
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Chapter 25 Oscillator (OSC) Table 25-5. Oscillator Modes Mode Frequency Range Low-frequency, high-gain fosc_lo (1 kHz) up to fosc_lo (32.
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Reset 25.8.2.3 High-Frequency, High-Gain Mode In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used. 25.8.2.
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Chapter 25 Oscillator (OSC) 25.10 Low Power Modes Operation When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and EREFSETN bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If ERCLKEN and EREFSTEN bits are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes.
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Interrupts K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 552 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 26 RTC Oscillator 26.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The RTC oscillator module provides the clock source for the RTC. The RTC oscillator module, in conjunction with an external crystal, generates a reference clock for the RTC. 26.1.
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RTC Signal Descriptions control Amplitude detector clk out for RTC EXTAL32 gm Rf XTAL32 C2 C1 PAD PAD Figure 26-1. RTC Oscillator Block Diagram 26.2 RTC Signal Descriptions The following table shows the user-accessible signals available for the RTC oscillator. See the chip-level specification to find out which signals are actually connected to the external pins. Table 26-1. RTC Signal Descriptions Signal EXTAL32 XTAL32 Description I/O Oscillator Input I Oscillator Output O 26.2.
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Chapter 26 RTC Oscillator 26.3 External Crystal Connections The connections with a crystal is shown in the following figure. External load capacitors and feedback resistor are not required. RTC Oscillator Module XTAL32 VSS EXTAL32 Crystal or Resonator Figure 26-2. Crystal Connections 26.4 Memory Map/Register Descriptions RTC oscillator control bits are part of the RTC registers. Refer to RTC_CR for more details. 26.
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Reset Overview 26.6 Reset Overview There is no reset state associated with the RTC oscillator. 26.7 Interrupts The RTC oscillator does not generate any interrupts. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 556 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 27 Flash Memory Controller (FMC) 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Flash Memory Controller (FMC) is a memory acceleration unit that provides: • an interface between the device and the dual-bank nonvolatile memory. Bank 0 consists of program flash memory, and bank 1 consists of FlexNVM. • buffers that can accelerate flash memory transfers. 27.1.
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Modes of operation 27.1.2 Features The FMC's features include: • Interface between the device and the dual-bank flash memory and FlexMemory: • 8-bit, 16-bit, and 32-bit read operations to program flash memory and FlexNVM used as data flash memory. • 8-bit, 16-bit, and 32-bit read and write operations to FlexNVM and FlexRAM used as EEPROM. • For bank 0: Read accesses to consecutive 32-bit spaces in memory return the second read data with no wait states. The memory returns 64 bits via the 32-bit bus access.
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Chapter 27 Flash Memory Controller (FMC) 27.4 Memory map and register descriptions The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings while a flash access is in progress can lead to non-deterministic behavior. Table 27-2.
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Memory map and register descriptions Table 27-3. Program visible cache registers Cache storage Based at offset Contents of 32-bit read Nomenclature Nomenclature example Tag 100h 13'h0, tag[18:6], 5'h0, valid In TAGVDWxSy, x denotes the way and y denotes the set. TAGVDW2S0 is the 13-bit tag and 1-bit valid for cache entry way 2, set 0.
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Chapter 27 Flash Memory Controller (FMC) FMC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4001_F160 Cache Tag Storage (FMC_TAGVDW3S0) 32 R/W 0000_0000h 27.4.7/573 4001_F164 Cache Tag Storage (FMC_TAGVDW3S1) 32 R/W 0000_0000h 27.4.7/573 4001_F168 Cache Tag Storage (FMC_TAGVDW3S2) 32 R/W 0000_0000h 27.4.7/573 4001_F16C Cache Tag Storage (FMC_TAGVDW3S3) 32 R/W 0000_0000h 27.4.
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Memory map and register descriptions FMC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4001_F260 Cache Data Storage (upper word) (FMC_DATAW1S4U) 32 R/W 0000_0000h 27.4.10/ 574 4001_F264 Cache Data Storage (lower word) (FMC_DATAW1S4L) 32 R/W 0000_0000h 27.4.11/ 575 4001_F268 Cache Data Storage (upper word) (FMC_DATAW1S5U) 32 R/W 0000_0000h 27.4.
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Chapter 27 Flash Memory Controller (FMC) FMC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 32 R/W 0000_0000h 27.4.12/ 575 4001_F2BC Cache Data Storage (lower word) (FMC_DATAW2S7L) 32 R/W 0000_0000h 27.4.13/ 576 4001_F2C0 Cache Data Storage (upper word) (FMC_DATAW3S0U) 32 R/W 0000_0000h 27.4.14/ 576 4001_F2C4 Cache Data Storage (lower word) (FMC_DATAW3S0L) 32 R/W 0000_0000h 27.4.
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Memory map and register descriptions 27.4.
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Chapter 27 Flash Memory Controller (FMC) FMC_PFAPR field descriptions (continued) Field 19 M3PFD Description Master 3 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 1 18 M2PFD Master 2 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master.
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Memory map and register descriptions FMC_PFAPR field descriptions (continued) Field Description 01 10 11 9–8 M4AP[1:0] Master 4 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 01 10 11 7–6 M3AP[1:0] This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master.
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Chapter 27 Flash Memory Controller (FMC) 27.4.
PAGE 568
Memory map and register descriptions FMC_PFB0CR field descriptions (continued) Field Description These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents are cleared. This field always reads as zero. Cache invalidation takes precedence over locking. The cache is invalidated by system reset.
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Chapter 27 Flash Memory Controller (FMC) FMC_PFB0CR field descriptions (continued) Field Description 0 1 2 B0DPE Do not cache instruction fetches. Cache instruction fetches. Bank 0 Data Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. 0 1 1 B0IPE Do not prefetch in response to data references. Enable prefetches in response to data references.
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Memory map and register descriptions FMC_PFB1CR field descriptions Field Description 31–28 B1RWSC[3:0] Bank 1 Read Wait State Control This read-only field defines the number of wait states required to access the bank 1 flash memory.
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Chapter 27 Flash Memory Controller (FMC) FMC_TAGVDW0Sn field descriptions Field Description 31–19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18–6 tag[18:6] 13-bit tag for cache entry 5–1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry 27.4.5 Cache Tag Storage (FMC_TAGVDW1Sn) The cache is a 4-way, set-associative cache with 8 sets.
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Memory map and register descriptions 27.4.6 Cache Tag Storage (FMC_TAGVDW2Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way.
PAGE 573
Chapter 27 Flash Memory Controller (FMC) 27.4.7 Cache Tag Storage (FMC_TAGVDW3Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way.
PAGE 574
Memory map and register descriptions FMC_DATAW0SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry 27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
PAGE 575
Chapter 27 Flash Memory Controller (FMC) FMC_DATAW1SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry 27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
PAGE 576
Memory map and register descriptions FMC_DATAW2SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry 27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
PAGE 577
Chapter 27 Flash Memory Controller (FMC) FMC_DATAW3SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry 27.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively.
PAGE 578
Functional description • These masters have write access to a portion of bank 1 when FlexNVM is used with FlexRAM as EEPROM. • For bank 0: • Prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2. • The cache is configured for least recently used (LRU) replacement for all four ways. • The cache is configured for data or instruction replacement. • The single-entry buffer is enabled. 27.5.
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Chapter 27 Flash Memory Controller (FMC) 2. the phase relationship of the core clock and flash clock at the time the read is requested. The ratio of the core clock to the flash clock is equal to the value of PFB0CR[B0RWSC] + 1 for bank 0 and to the value of PFB1CR[B1RWSC] + 1 for bank 1. For example, in a system with a 4:1 core-to-flash clock ratio, a read that does not hit in the speculation buffer or the cache can take between 4 and 7 core clock cycles to complete.
PAGE 580
Initialization and application information • The core requests four sequential longwords in back-to-back requests, meaning there are no core cycle delays except for stalls waiting for flash memory data to be returned. • None of the data is already stored in the cache or speculation buffer. In this scenario, the sequence of events for accessing the four longwords is as follows: 1. The first longword read requires 4 to 7 core clocks. See Wait states for more information. 2.
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Chapter 28 Flash Memory Module (FTFL) 28.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter.
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Introduction states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. 28.1.1 Features The flash memory module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device. 28.1.1.
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Chapter 28 Flash Memory Module (FTFL) 28.1.1.
PAGE 584
Introduction Interrupt Program flash Status registers Register access Memory controller Control registers To MCU's flash controller FlexNVM Data flash FlexRAM EEPROM backup Figure 28-1. Flash Block Diagram 28.1.3 Glossary Command write sequence — A series of MCU writes to the flash FCCOB register group that initiates and controls the execution of flash algorithms that are built into the flash memory module.
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Chapter 28 Flash Memory Module (FTFL) EEPROM backup data record — The EEPROM backup data record is comprised of a 2-bit status field, a 14-bit address field, and a 16-bit data field found in EEPROM backup data memory which is used by the EEPROM filing system. If the status field indicates a record is valid, the data field is mirrored in the FlexRAM at a location determined by the address field.
PAGE 586
External Signal Description NVM Special Mode — An NVM mode enabling external, off-chip access to the memory resources in the flash memory module. A reduced flash command set is available when the MCU is secured. See the Chip Configuration details for information on when this mode is used. Phrase — 64 bits of data with an aligned phrase having byte-address[2:0] = 000. Longword — 32 bits of data with an aligned longword having byte-address[1:0] = 00.
PAGE 587
Chapter 28 Flash Memory Module (FTFL) 28.3.1 Flash Configuration Field Description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the flash memory module. Flash Configuration Field Byte Address Size (Bytes) Field Description 0x0_0400 - 0x0_0407 8 Backdoor Comparison Key.
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Memory Map and Registers 28.3.2.1 Program Once Field The Program Once Field in the program flash IFR provides 64 bytes of user data storage separate from the program flash main array. The user can program the Program Once Field one time only as there is no program flash IFR erase mechanism available to the user. The Program Once Field can be read any number of times.
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Chapter 28 Flash Memory Module (FTFL) Table 28-2. EEPROM Data Set Size Field Description Field Description 7-4 This read-only bitfield is reserved and must always be written as one. Reserved EEPROM Size — Encoding of the total available FlexRAM for EEPROM use. 3-0 NOTE: EEESIZE must be 0 bytes (1111b) when the FlexNVM partition code (FlexNVM Partition Code) is set to 'No EEPROM'.
PAGE 590
Memory Map and Registers Table 28-4. FlexNVM Partition Code Field Description Field 7-4 Description This read-only bitfield is reserved and must always be written as one. Reserved 3-0 DEPART FlexNVM Partition Code — Encoding of the data flash / EEPROM backup split within the FlexNVM memory block. FlexNVM memory not partitioned for data flash will be used to store EEPROM records.
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Chapter 28 Flash Memory Module (FTFL) FTFL memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_0000 Flash Status Register (FTFL_FSTAT) 8 R/W 00h 28.34.1/ 592 4002_0001 Flash Configuration Register (FTFL_FCNFG) 8 R/W 00h 28.34.2/ 593 4002_0002 Flash Security Register (FTFL_FSEC) 8 R Undefined 28.34.3/ 595 4002_0003 Flash Option Register (FTFL_FOPT) 8 R Undefined 28.34.
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Memory Map and Registers 28.34.1 Flash Status Register (FTFL_FSTAT) The FSTAT register reports the operational status of the flash memory module. The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable.
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Chapter 28 Flash Memory Module (FTFL) FTFL_FSTAT field descriptions (continued) Field Description CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the ACCERR bit has no effect.
PAGE 594
Memory Map and Registers FTFL_FCNFG field descriptions Field 7 CCIE Description Command Complete Interrupt Enable The CCIE bit controls interrupt generation when a flash command completes. 0 1 6 RDCOLLIE Read Collision Error Interrupt Enable The RDCOLLIE bit controls interrupt generation when a flash memory read collision error occurs. 0 1 5 ERSAREQ Command complete interrupt disabled Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
PAGE 595
Chapter 28 Flash Memory Module (FTFL) FTFL_FCNFG field descriptions (continued) Field Description 0 1 0 EEERDY FlexRAM is not available for traditional RAM access. FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations. This flag indicates if the EEPROM backup data has been copied to the FlexRAM and is therefore available for read access.
PAGE 596
Memory Map and Registers FTFL_FSEC field descriptions (continued) Field 5–4 MEEN Description Mass Erase Enable Bits Enables and disables mass erase capability of the flash memory module. The state of the MEEN bits is only relevant when the SEC bits are set to secure outside of NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does not matter.
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Chapter 28 Flash Memory Module (FTFL) Address: 4002_0000h base + 3h offset = 4002_0003h Bit 7 6 5 4 Read 3 2 1 0 x* x* x* x* OPT Write Reset x* x* x* x* * Notes: • x = Undefined at reset. FTFL_FOPT field descriptions Field 7–0 OPT Description Nonvolatile Option These bits are loaded from flash to this register at reset. Refer to the device's Chip Configuration details for the definition and use of these bits. 28.34.
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Memory Map and Registers FTFL_FCCOBn field descriptions (continued) Field Description NOTE: The command parameter table is written in terms of FCCOB Number (which is equivalent to the byte number). This number is a reference to the FCCOB register name and is not the register address.
PAGE 599
Chapter 28 Flash Memory Module (FTFL) During the reset sequence, the FPROT registers are loaded with the contents of the program flash protection bytes in the Flash Configuration Field as indicated in the following table.
PAGE 600
Memory Map and Registers 28.34.7 EEPROM Protection Register (FTFL_FEPROT) The FEPROT register defines which EEPROM regions of the FlexRAM are protected against program and erase operations. Protected EEPROM regions cannot have their content changed by writing to it. Unprotected regions can be changed by writing to the FlexRAM. Address: 4002_0000h base + 16h offset = 4002_0016h Bit Read Write Reset 7 6 5 4 3 2 1 0 x* x* x* x* EPROT x* x* x* x* * Notes: • x = Undefined at reset.
PAGE 601
Chapter 28 Flash Memory Module (FTFL) 28.34.8 Data Flash Protection Register (FTFL_FDPROT) The FDPROT register defines which data flash regions are protected against program and erase operations. Protected Flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any flash command. Unprotected regions can be changed by both program and erase operations.
PAGE 602
Functional Description 28.4 Functional Description The following sections describe functional details of the flash memory module. 28.4.1 Flash Protection Individual regions within the flash memory can be protected from program and erase operations.
PAGE 603
Chapter 28 Flash Memory Module (FTFL) FlexNVM 0x0_0000 EEPROM backup size (DEPART) Last data flash address Data flash size / 8 DPROT0 Data flash size / 8 DPROT1 Data flash size / 8 DPROT2 Data flash size / 8 DPROT3 Data flash size / 8 DPROT4 Data flash size / 8 DPROT5 Data flash size / 8 DPROT6 Data flash size / 8 DPROT7 EEPROM backup Last FlexNVM address Figure 28-27.
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Functional Description 28.4.2 FlexNVM Description This section describes the FlexNVM memory. 28.4.2.1 FlexNVM Block Partitioning for FlexRAM The user can configure the FlexNVM block as either: • Basic data flash, • EEPROM flash records to support the built-in EEPROM feature, or • A combination of both. The user's FlexNVM configuration choice is specified using the Program Partition command described in Program Partition Command.
PAGE 605
Chapter 28 Flash Memory Module (FTFL) configured for EEPROM (see Set FlexRAM Function Command). The EEPROM partition grows upward from the bottom of the FlexRAM address space. 2. Data flash partition (DEPART) — The amount of FlexNVM memory used for data flash can be programmed from 0 bytes (all of the FlexNVM block is available for EEPROM backup) to the maximum size of the FlexNVM block (see Table 28-4). 3.
PAGE 606
Functional Description and copies the newest data to FlexRAM. The FSTAT[CCIF] and FCNFG[EEERDY] bits are set after data from all valid EEPROM data records is copied to the FlexRAM. After the CCIF bit is set, the FlexRAM is available for read or write access. When configured for EEPROM use, writes to an unprotected location in FlexRAM invokes the EEPROM file system to program a new EEPROM data record in the EEPROM backup memory in a round-robin fashion.
PAGE 607
Chapter 28 Flash Memory Module (FTFL) • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • nnvmcycd — data flash cycling endurance Figure 28-31. EEPROM backup writes to FlexRAM 28.4.3 Interrupts The flash memory module can generate interrupt requests to the MCU upon the occurrence of various flash events. These interrupt events and their associated status and control bits are shown in the following table. Table 28-30.
PAGE 608
Functional Description Note Vector addresses and their relative interrupt priority are determined at the MCU level. 28.4.4 Flash Operation in Low-Power Modes 28.4.4.1 Wait Mode When the MCU enters wait mode, the flash memory module is not affected. The flash memory module can recover the MCU from wait via the command complete interrupt (see Interrupts). 28.4.4.
PAGE 609
Chapter 28 Flash Memory Module (FTFL) The MCU must not read from the flash memory while commands are running (as evidenced by CCIF=0) on that block. Read data cannot be guaranteed from a flash block while any command is processing within that block. The block arbitration logic detects any simultaneous access and reports this as a read collision error (see the FSTAT[RDCOLERR] bit). 28.4.
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Functional Description • The command write sequence used to set flash command parameters and launch execution • A description of all flash commands available 28.4.9.1 Command Write Sequence Flash commands are specified using a command write sequence illustrated in Figure 28-32. The flash memory module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled.
PAGE 611
Chapter 28 Flash Memory Module (FTFL) If the parameter check fails, the FSTAT[ACCERR] (access error) flag is set. ACCERR reports invalid instruction codes and out-of bounds addresses. Usually, access errors suggest that the command was not set-up with valid parameters in the FCCOB register group. Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, the FSTAT[FPVIOL] (protection error) flag is set.
PAGE 612
Functional Description START Read: FSTAT register FCCOB Availability Check no CCIF = ‘1’? Previous command complete? yes Access Error and Protection Violation Check Results from previous command yes ACCERR/ FPVIOL Set? Clear the old errors Write 0x30 to FSTAT register no Write to the FCCOB registers to load the required command parameter. More Parameters? yes no Clear the CCIF to launch the command Write 0x80 to FSTAT register EXIT Figure 28-32.
PAGE 613
Chapter 28 Flash Memory Module (FTFL) FCMD Command Program flash Data flash 0x01 Read 1s Section × × FlexRAM Verify that a given number of program flash or data flash locations from a starting address are erased. 0x02 Program Check × × Tests previouslyprogrammed locations at margin read levels. 0x03 Read Resource IFR, ID IFR Read 4 bytes from program flash IFR, data flash IFR, or version ID. 0x06 Program Longword × × Program 4 bytes in a program flash block or a data flash block.
PAGE 614
Functional Description FCMD Command Program flash 0x43 Program Once IFR 0x44 Erase All Blocks × Data flash FlexRAM Function One-time program of 4 bytes of a dedicated 64-byte field in the program flash IFR. × × Erase all program flash blocks, data flash blocks, FlexRAM, EEPROM backup data records, and data flash IFR. Then, verify-erase and release MCU security. NOTE: × An erase is only possible when all memory locations are unprotected.
PAGE 615
Chapter 28 Flash Memory Module (FTFL) 28.4.9.3 Flash Commands by Mode The following table shows the flash commands that can be executed in each flash operating mode. Table 28-31.
PAGE 616
Functional Description Table 28-32. Allowed Simultaneous Memory Operations Program Flash Read Read OK Program OK Sector Erase OK Read FlexRAM R-Write2 Read FlexRAM Program Sector Erase OK OK E-Write1 R-Write2 OK OK OK3 — OK OK OK OK — OK OK — OK OK OK — — OK Read OK — Read E-Write1 Sector Erase — Program Program flash Sector Erase Data flash Program Data Flash OK OK OK — OK OK OK OK — 1.
PAGE 617
Chapter 28 Flash Memory Module (FTFL) The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. The 'user' margin is a small delta to the normal read reference level. 'User' margin levels can be employed to check that flash memory contents have adequate margin for normal level read operations.
PAGE 618
Functional Description • program flash (=0) block • data flash (=1) block CAUTION Flash data must be in the erased state before being programmed. Cumulative programming of bits (adding more zeros) is not allowed. 28.4.11.1 Read 1s Block Command The Read 1s Block command checks to see if an entire program flash or data flash block has been erased to the specified margin level. The FCCOB flash address bits determine which logical block is erase-verified. Table 28-33.
PAGE 619
Chapter 28 Flash Memory Module (FTFL) Table 28-35.
PAGE 620
Functional Description Upon clearing CCIF to launch the Read 1s Section command, the flash memory module sets the read margin for 1s according to Table 28-38 and then reads all locations within the specified section of flash memory. If the flash memory module fails to read all 1s (i.e. the flash section is not erased), the FSTAT(MGSTAT0) bit is set. The CCIF flag sets after the Read 1s Section operation completes. Table 28-38.
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Chapter 28 Flash Memory Module (FTFL) Upon clearing CCIF to launch the Program Check command, the flash memory module sets the read margin for 1s according to Table 28-41, reads the specified longword, and compares the actual read data to the expected data provided by the FCCOB. If the comparison at margin-1 fails, the MGSTAT0 bit is set. The flash memory module then sets the read margin for 0s, re-reads, and compares again. If the comparison at margin-0 fails, the MGSTAT0 bit is set.
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Functional Description Table 28-43. Read Resource Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x03 (RDRSRC) 1 Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0]1 Returned Values 4 Read Data [31:24] 5 Read Data [23:16] 6 Read Data [15:8] 7 Read Data [7:0] User-provided values 8 Resource Select Code (see Table 28-44) 1. Must be longword aligned (Flash address [1:0] = 00). Table 28-44.
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Chapter 28 Flash Memory Module (FTFL) CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-toback program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device. Table 28-46.
PAGE 624
Functional Description Table 28-47. Program Longword Command Error Handling (continued) Error Condition Error Bit Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 28.4.11.6 Erase Flash Block Command The Erase Flash Block operation erases all addresses in a single program flash or data flash block. Table 28-48.
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Chapter 28 Flash Memory Module (FTFL) 28.4.11.7 Erase Flash Sector Command The Erase Flash Sector operation erases all addresses in a flash sector. Table 28-50. Erase Flash Sector Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x09 (ERSSCR) 1 Flash address [23:16] in the flash sector to be erased 2 Flash address [15:8] in the flash sector to be erased 3 Flash address [7:0]1, 2 in the flash sector to be erased 1. For program flash:Must be phrase aligned (flash address [2:0] = 000).
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Functional Description If an Erase Flash Sector operation effectively completes before the flash memory module detects that a suspend request has been made, the flash memory module clears the ERSSUSP bit prior to setting CCIF. When an Erase Flash Sector operation has been successfully suspended, the flash memory module sets CCIF and leaves the ERSSUSP bit set.
PAGE 627
Chapter 28 Flash Memory Module (FTFL) Enter with CCIF = 1 Command Initiation ERSSCR Command (Write FCCOB) Memory Controller Command Processing Launch/Resume Command (Clear CCIF) Yes SUSPACK=1 Next Command (Write FCCOB) Yes CCIF = 1? Start New No No Interrupt? No DONE? Request Suspend (Set ERSSUSP) Yes No ERSSUSP=1? CCIF = 1? Restore Erase Algo Clear SUSPACK = 0 Execute Yes No Resume ERSSCR No Yes Save Erase Algo Clear ERSSUSP Yes Service Interrupt (Read Flash) ERSSCR Suspended ERSSUS
PAGE 628
Functional Description 28.4.11.8 Program Section Command The Program Section operation programs the data found in the section program buffer to previously erased locations in the flash memory using an embedded algorithm. Data is preloaded into the section program buffer by writing to the FlexRAM while it is set to function as traditional RAM (see Flash Sector Programming). The section program buffer is limited to the lower half of the RAM.
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Chapter 28 Flash Memory Module (FTFL) The starting address must be unprotected (see the description of the FPROT and FDPROT registers) to permit execution of the Program Section operation. Programming, which is not allowed to cross a flash sector boundary, continues until all requested phrases or longwords have been programmed. The Program Section command also verifies that after programming, all bits requested to be programmed are programmed.
PAGE 630
Functional Description 5. If a flash sector is larger than half the FlexRAM, repeat steps 3 and 4 until the sector is completely programmed. 6. To program additional flash sectors, repeat steps 2 through 4. 7. To restore EEPROM functionality, execute the Set FlexRAM Function command to make the FlexRAM available as EEPROM. 28.4.11.
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Chapter 28 Flash Memory Module (FTFL) Table 28-57. Read 1s All Blocks Command Error Handling Error Condition Error Bit An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] 28.4.11.10 Read Once Command The Read Once command provides read access to a reserved 64-byte field located in the program flash IFR (see Program Flash IFR Map and Program Once Field). Access to this field is via 16 records, each 4 bytes long.
PAGE 632
Functional Description 28.4.11.11 Program Once Command The Program Once command enables programming to a reserved 64-byte field in the program flash IFR (see Program Flash IFR Map and Program Once Field). Access to the Program Once field is via 16 records, each 4 bytes long. The Program Once field can be read using the Read Once command (see Read Once Command) or using the Read Resource command (see Read Resource Command).
PAGE 633
Chapter 28 Flash Memory Module (FTFL) 28.4.11.12 Erase All Blocks Command The Erase All Blocks operation erases all flash memory, initializes the FlexRAM, verifies all memory contents, and releases MCU security. Table 28-62.
PAGE 634
Functional Description erase-all request is reflected in the FCNFG[ERSAREQ] bit. The FCNFG[ERSAREQ] bit is cleared once the operation completes and the normal FSTAT error reporting is available as described in Erase All Blocks Command. 28.4.11.13 Verify Backdoor Access Key Command The Verify Backdoor Access Key command only executes if the mode and security conditions are satisfied (see Flash Commands by Mode).
PAGE 635
Chapter 28 Flash Memory Module (FTFL) Table 28-65. Verify Backdoor Access Key Command Error Handling Error Condition Error Bit The supplied key is all-0s or all-Fs FSTAT[ACCERR] An incorrect backdoor key is supplied FSTAT[ACCERR] Backdoor key access has not been enabled (see the description of the FSEC register) FSTAT[ACCERR] This command is launched and the backdoor key has mismatched since the last power down reset FSTAT[ACCERR] 28.4.11.
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Functional Description Table 28-67. Valid EEPROM Data Set Size Codes (continued) EEPROM Data Size Code (FCCOB4)1 EEPROM Data Set Size (Bytes) FCCOB4[5:4] FCCOB4[EEESIZE] 11 0x7 128 11 0x6 256 11 0x5 512 11 0x4 1024 11 0x3 2048 1. FCCOB4[7:6] = 00 2. EEPROM Data Set Size must be set to 0 bytes when the FlexNVM Partition Code is set for no EEPROM. Table 28-68.
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Chapter 28 Flash Memory Module (FTFL) Table 28-69.
PAGE 638
Functional Description After clearing CCIF to launch the Set FlexRAM Function command, the flash memory module sets the function of the FlexRAM based on the FlexRAM Function Control Code. When making the FlexRAM available as traditional RAM, the flash memory module clears the FCNFG[EEERDY] and FCNFG[RAMRDY] flags, overwrites the contents of the entire FlexRAM with a background pattern of all ones, and sets the FCNFG[RAMRDY] flag.
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Chapter 28 Flash Memory Module (FTFL) Table 28-73. FSEC register fields FSEC field Description KEYEN Backdoor Key Access MEEN Mass Erase Capability FSLACC Freescale Factory Access SEC MCU security 28.4.12.1 Flash Memory Access by Mode and Security The following table summarizes how access to the flash memory module is affected by security and operating mode. Table 28-74.
PAGE 640
Functional Description Backdoor Access Key command as valid comparison values. While the Verify Backdoor Access Key command is active, program flash memory is not available for read access and returns invalid data. The user code stored in the program flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
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Chapter 28 Flash Memory Module (FTFL) CCIF is cleared throughout the reset sequence. The flash memory module holds off CPU access during the reset sequence. Flash reads are possible when the hold is removed. Completion of the reset sequence is marked by setting CCIF which enables flash user commands. If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed.
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Functional Description K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 642 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) 29.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This chapter describes external bus data transfer operations and error conditions. It describes transfers initiated by the core processor (or any other bus master) and includes detailed timing diagrams showing the interaction of signals in supported bus operations. 29.1.
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Signal descriptions 29.1.
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Chapter 29 External Bus Interface (FlexBus) Table 29-1. FlexBus signal descriptions (continued) Signal I/O Function FB_CS5–FB_CS0 O General Purpose Chip-Selects—Indicate which external memory or peripheral is selected. A particular chip-select is asserted when the transfer address is within the external memory's or peripheral's address space, as defined in CSAR[BA] and CSMR[BAM]. FB_BE_31_24 O Byte Enables—Indicate that data is to be latched or driven onto a specific byte lane of the data bus.
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Signal descriptions Table 29-1. FlexBus signal descriptions (continued) Signal I/O Function FB_TSIZ1–FB_TSIZ0 O Transfer Size—Indicates (along with FB_TBST) the data transfer size of the current bus operation. The interface supports 8-, 16-, and 32-bit operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. • 00b = 4 bytes • 01b = 1 byte • 10b = 2 bytes • 11b = 16 bytes (line) For misaligned transfers, FB_TSIZ1–FB_TSIZ0 indicate the size of each transfer.
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Chapter 29 External Bus Interface (FlexBus) Table 29-1. FlexBus signal descriptions (continued) Signal I/O FB_TA I Function Transfer Acknowledge—Indicates that the external data transfer is complete. When FB_TA is asserted during a read transfer, FlexBus latches the data and then terminates the transfer. When FB_TA is asserted during a write transfer, the transfer is terminated. If auto-acknowledge is disabled (CSCR[AA] = 0), the external memory or peripheral drives FB_TA to terminate the transfer.
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Memory Map/Register Definition FB memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4000_C000 Chip Select Address Register (FB_CSAR0) 32 R/W 0000_0000h 29.3.1/648 4000_C004 Chip Select Mask Register (FB_CSMR0) 32 R/W 0000_0000h 29.3.2/649 4000_C008 Chip Select Control Register (FB_CSCR0) 32 R/W 0000_0000h 29.3.3/650 4000_C00C Chip Select Address Register (FB_CSAR1) 32 R/W 0000_0000h 29.3.
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Chapter 29 External Bus Interface (FlexBus) FB_CSARn field descriptions (continued) Field Description NOTE: Because the FlexBus module is one of the slaves connected to the crossbar switch, it is only accessible within a certain memory range. See the chip memory map for the applicable FlexBus "expansion" address range for which the chip-selects can be active. Set the CSARn and CSMRn registers appropriately before accessing this region. 15–0 Reserved This field is reserved.
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Memory Map/Register Definition FB_CSMRn field descriptions (continued) Field Description NOTE: At reset, no chip-select other than FB_CS0 can be used until CSMR0[V] is 1b. Afterward, the FB_CS [5:0] signals function as programmed. 0 1 Chip-select is invalid. Chip-select is valid. 29.3.3 Chip Select Control Register (FB_CSCRn) Controls the auto-acknowledge, address setup and hold times, port size, burst capability, and number of wait states for the associated chip select.
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Chapter 29 External Bus Interface (FlexBus) FB_CSCRn field descriptions (continued) Field Description Used only when the SWSEN bit is 1b. Specifies the number of wait states inserted before an internal transfer acknowledge is generated for a burst transfer (except for the first termination, which is controlled by WS). 25–24 Reserved 23 SWSEN This field is reserved. This read-only field is reserved and always has the value 0.
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Memory Map/Register Definition FB_CSCRn field descriptions (continued) Field 15–10 WS 9 BLS Description Wait States Specifies the number of wait states inserted after FlexBus asserts the associated chip-select and before an internal transfer acknowledge is generated (WS = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states). Byte-Lane Shift Specifies if data on FB_AD appears left-aligned or right-aligned during the data phase of a FlexBus access. 0 1 8 AA Not shifted.
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Chapter 29 External Bus Interface (FlexBus) FB_CSCRn field descriptions (continued) Field Description 3 BSTW Burst-Write Enable Specifies whether burst writes are enabled for memory associated with each chip select. 0 1 2–0 Reserved Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. Enabled.
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Functional description FB_CSPMCR field descriptions (continued) Field 23–20 GROUP3 Description FlexBus Signal Group 3 Multiplex control Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals. 0000 0001 0010 Any other value 19–16 GROUP4 FlexBus Signal Group 4 Multiplex control Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
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Chapter 29 External Bus Interface (FlexBus) 29.4.2 Address comparison When a bus cycle is routed to FlexBus, FlexBus compares the transfer address to the base address and base address mask. This table describes how FlexBus decides to assert a chip-select and complete the bus cycle based on the address comparison. When the transfer address Then FlexBus Asserts the appropriate chip-select, generating a FlexBus bus cycle as defined in the appropriate CSCR.
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Functional description 29.4.6 Data transfer signals Data transfers between FlexBus and the external memory or peripheral involve these signals: • Address/data bus (FB_AD31–FB_AD0 ) • Control signals (FB_TS/FB_ALE, FB_TA, FB_CSn, FB_OE, FB_R/W, FB_BEn) • Attribute signals (FB_TBST, FB_TSIZ1–FB_TSIZ0) 29.4.
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Chapter 29 External Bus Interface (FlexBus) Byte Select FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 External Data Bus 32-Bit Port Memory 16-Bit Port Memory 8-Bit Port Memory FB_D31– FB_D24 FB_D23– FB_D16 Byte 3 Byte 2 Byte 1 Byte 0 Byte 3 Byte 2 FB_BE_7_0 FB_D15– FB_D8 Byte 1 FB_D7– FB_D0 Byte 0 Driven with address values Byte 0 Byte 1 Driven with address values Byte 2 Byte 3 Figure 29-23.
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Functional description 29.4.9.1 FlexBus multiplexed operating modes for CSCRn[BLS]=0 This table shows the supported combinations of address and data bus widths when CSCRn[BLS] is 0b. FB_AD 8-bit 16-bit 32-bit Port size and phase 31–24 23–16 15–8 Address phase Address Data phase Data Address phase Address Data phase Data 7–0 Address Address phase Address Data phase Data Address 29.4.9.
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Chapter 29 External Bus Interface (FlexBus) S0 Next Cycle Wait States S3 S1 S2 The states are described in this table. State Cycle Description S0 All The read or write cycle is initiated.
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Functional description Note Throughout this section: • FB_D[X] indicates a 32-, 16-, or 8-bit wide data bus • FB_A[Y] indicates an address bus that can be 32, 24, or 16 bits wide. 29.4.11.1 Basic Read Bus Cycle During a read cycle, the MCU receives data from memory or a peripheral device. The following figure shows a read cycle flowchart. Microcontroller System 1. Set FB_R/W to read. 2. Place address on the external address signals. 3. Assert transfer start. 1. Decode address. 1. Negate transfer start.
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Chapter 29 External Bus Interface (FlexBus) The address and data busses are muxed between the FlexBus and another module. At the end of the read bus cycles the address signals are indeterminate. FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-26. Basic Read-Bus Cycle 29.4.11.2 Basic Write Bus Cycle During a write cycle, the device sends data to memory or to a peripheral device.
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Functional description External Memory/Peripheral FlexBus 1. Set FB_R/W to write. 2. Place address on the external address signals. 3. Assert transfer start. 1. Decode address. 1. Negate transfer start. 2. Assert FB_CSn. 3. Drive data. 1. Select the appropriate slave device. 1. FlexBus asserts internal FB_TA (auto acknowledge/internal termination). 2. Latch data on the external address signals. 2. Sample FB_TA low. 3. Assert FB_TA (external termination). 1. Start next cycle. 1.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-28. Basic Write-Bus Cycle 29.4.11.3 Bus Cycle Sizing This section shows timing diagrams for various port size scenarios. 29.4.11.3.
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Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 01 Figure 29-29. Single Byte-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:24]. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 664 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=01 Figure 29-30. Single Byte-Write Transfer 29.4.11.3.2 Bus Cycle Sizing—Word Transfer, 16-bit Device, No Wait States The following figure illustrates the basic word read transfer to a 16-bit device with no wait states. • The address is driven on the full FB_AD[31:8] bus in the first clock.
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Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 10 Figure 29-31. Single Word-Read Transfer The following figure shows the similar configuration for a write transfer. The data is driven from the second clock on FB_AD[31:16]. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 666 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=10 Figure 29-32. Single Word-Write Transfer 29.4.11.3.3 Bus Cycle Sizing—Longword Transfer, 32-bit Device, No Wait States The following figure depicts a longword read from a 32-bit device. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 Figure 29-33. Longword-Read Transfer The following figure illustrates the longword write to a 32-bit device. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 668 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ=00 Figure 29-34. Longword-Write Transfer 29.4.11.4 Timing Variations The FlexBus module has several features that can change the timing characteristics of a basic read- or write-bus cycle to provide additional address setup, address hold, and time for a device to provide or latch data. 29.4.11.4.
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Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-35. Basic Read-Bus Cycle (No Wait States) K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 670 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-36. Basic Write-Bus Cycle (No Wait States) If wait states are used, the S1 state repeats continuously until the chip-select autoacknowledge unit asserts internal transfer acknowledge or the external FB_TA is recognized as asserted.
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Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-37. Read-Bus Cycle (One Wait State) K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 672 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-38. Write-Bus Cycle (One Wait State) 29.4.11.4.2 Address Setup and Hold The timing of the assertion and negation of the chip selects, byte selects, and output enable can be programmed on a chip-select basis.
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Functional description FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-39. Read-Bus Cycle with Two-Clock Address Setup (No Wait States) K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 674 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-40. Write-Bus Cycle with Two Clock Address Setup (No Wait States) In addition to address setup, a programmable address hold option for each chip select exists. Address and attributes can be held one to four clocks after chip-select, byteselects, and output-enable negate.
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Functional description FB_CLK Address FB_A[Y] FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-41. Read Cycle with Two-Clock Address Hold (No Wait States) K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 676 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-42. Write Cycle with Two-Clock Address Hold (No Wait States) The following figure shows a bus cycle using address setup, wait states, and address hold. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Functional description FB_CLK FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-43. Write Cycle with Two-Clock Address Setup and Two-Clock Hold (One Wait State) 29.4.12 Burst cycles The chip can be programmed to initiate burst cycles if its transfer size exceeds the port size of the selected destination. The initiation of a burst cycle is encoded on the transfer size pins (FB_TSIZ[1:0]).
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Chapter 29 External Bus Interface (FlexBus) 29.4.12.2 Transfer size and port size translation With bursting disabled, any transfer larger than the port size breaks into multiple individual transfers (e.g. ). With bursting enabled, any transfer larger than the port size results in a burst cycle of multiple beats (e.g. ). The following table shows the result of such transfer translations.
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Functional description FB_CLK FB_A[Y] FB_D[X] Add+1 Address Address Data Add+2 Data Add+3 Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ = 11 29.4.12.4 32-bit-Write burst to 8-Bit port 3-1-1-1 (no wait states) The following figure shows a 32-bit write to an 8-bit external chip with burst enabled. The transfer results in a 4-beat burst and the data is driven on FB_AD[31:24]. The transfer size is driven at 32-bit (00b) throughout the bus cycle.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] FB_D[X] Address Address Add+1 Data Add+2 Data Add+3 Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ 29.4.12.5 32-bit-write burst-inhibited to 8-bit port (no wait states) The following figure shows a 32-bit write to an 8-bit device with burst inhibited. The transfer results in four individual transfers.
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Functional description FB_CLK FB_A[Y] Address FB_D[X] Add Add+1 Data Add+1 Add+2 Data Add+2 Data Add+3 Add+3 Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TBST FB_TSIZ[1:0] TSIZ = 01 TSIZ = 00 29.4.12.6 32-bit-read burst from 8-bit port 3-2-2-2 (one wait state) The following figure illustrates another read burst transfer, but in this case a wait state is added between individual beats.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] FB_D[X] Address Address Data Add+1 Data Add+2 Data Add+3 Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ = 00 29.4.12.7 32-bit-write burst to 8-bit port 3-2-2-2 (one wait state) The following figure illustrates a write burst transfer with one wait state. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Functional description FB_CLK FB_A[Y] Address FB_D[X] Add+1 Address Add+2 Data Data Add+3 Data Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ = 00 29.4.12.8 32-bit-read burst from 8-bit port 3-1-1-1 (address setup and hold) If address setup and hold are used, only the first and last beat of the burst cycle are affected. The following figure shows a read cycle with one clock of address setup and address hold.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] FB_D[X] Add+1 Address Address Data Data Add+2 Data Add+3 Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ=11 29.4.12.9 32-bit-write burst to 8-bit port 3-1-1-1 (address setup and hold) The following figure shows a write cycle with one clock of address setup and address hold. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Functional description FB_CLK FB_A[Y] FB_D[X] Address Address Add+1 Data Add+2 Data Data Add+3 Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ=11 29.4.13 Extended Transfer Start/Address Latch Enable The FB_TS/FB_ALE signal indicates that a bus transaction has begun and the address and attributes are valid. By default, the FB_TS/FB_ALE signal asserts for a single bus clock cycle.
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Chapter 29 External Bus Interface (FlexBus) FB_CLK FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB_BE/BWEn AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 29-44. Read-Bus Cycle with CSCRn[EXTS] = 1 (One Wait State) 29.4.
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Initialization/Application Information 29.5 Initialization/Application Information 29.5.1 Initializing a chip-select To initialize a chip-select: 1. Write to the associated CSAR. 2. Write to the associated CSCR. 3. Write to the associated CSMR, including writing 1b to the Valid field (CSMRn[V]). 29.5.2 Reconfiguring a chip-select To reconfigure a previously-used chip-select: 1. Invalidate the chip-select by writing 0b to the associated CSMR's Valid field (CSMRn[V]). 2. Write to the associated CSAR. 3.
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Chapter 30 EzPort 30.1 Overview NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The EzPort module is a serial flash programming interface that allows In-System Programming (ISP) of flash memory contents on a 32 bit general-purpose microcontroller.
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Overview EzPort Enabled G EZP_CS EZP_CK Flash Controller EzPort EZP_D EZP_Q Reset Flash Memory Reset Out Reset Controller Microcontroller Core Figure 30-1. EzPort block diagram 30.1.2 Features EzPort includes the following features: • Serial interface that is compatible with a subset of the SPI format. • Ability to read, erase, and program flash memory. • Ability to reset the microcontroller, allowing it to boot from the flash memory after the memory has been configured. 30.1.
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Chapter 30 EzPort The EzPort provides a simple interface to connect an external device to the flash memory on board a 32 bit microcontroller. The interface itself is compatible with the SPI interface, with the EzPort operating as a slave, running in either of the two following modes. The data is transmitted with the most significant bit first. • CPOL = 0, CPHA = 0 • CPOL = 1, CPHA = 1 Commands are issued by the external device to erase, program, or read the contents of the flash memory.
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Command definition 30.2.2 EzPort Chip Select (EZP_CS) EZP_CS is the chip select for signaling the start and end of serial transfers. If, while EZP_CS is asserted, the microcontroller's reset out signal is negated, EzPort is enabled out of reset; otherwise it is disabled. After EzPort is enabled, asserting EZP_CS commences a serial data transfer, which continues until EZP_CS is negated again.
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Chapter 30 EzPort Table 30-2. EzPort commands (continued) Command Description Code Address Bytes Data Bytes Accepted when secure? FAST_RDFCCOB Read FCCOB registers at high speed 0xBB 0 1 - 122 No WRFLEXRAM Write FlexRAM 0xBC 31 4 No 0xBD 31 1+ No 0xBE 31 1+2 No RDFLEXRAM FAST_RDFLEXRAM Read FlexRAM Read FlexRAM at high speed 1. 2. 3. 4. Address must be 32-bit aligned (two LSBs must be zero). One byte of dummy data must be shifted in before valid data is shifted out.
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Command definition Table 30-3. EzPort status register R 7 6 FS WEF 0/11 0 5 4 3 2 1 0 FLEXRAM BEDIS WEN WIP 0/12 0/13 0 14 W Reset: 0 0 1. Reset value reflects the status of flash security out of reset. 2. Reset value reflects FlexNVM flash partitioning. If FlexNVM flash has been paritioned for EEPROM, this field is set immediately after reset. Note that FLEXRAM is cleared after the EzPort initialization sequence completes, as indicated by clearing of WIP. 3.
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Chapter 30 EzPort Table 30-4. EzPort status register field description (continued) Field Description 6 Write error flag WEF Indicates whether there has been an error while executing a write command (SP, SE, BE, WRFCCOB, or WRFLEXRAM). The WEF flag will set if Flash Access Error Flag (ACCERR), Flash Protection Violation (FPVIOL), or Memory Controller Command Completion Status (MGSTAT0) inside the flash memory is set at the completion of the write command.
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Command definition 30.3.1.6 Section Program The Section Program (SP) command programs up to one section of flash memory that has previously been erased. Please see the Flash Memory chapter for a definition of section size. The starting address of the memory to program is sent after the command word and must be a 64-bit aligned address with the three LSBs being zero). As data is shifted in, the EzPort buffers the data in FlexRAM before executing an SP command within the flash.
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Chapter 30 EzPort 30.3.1.8 Bulk Erase The Bulk Erase (BE) command erases the entire contents of flash memory, ignoring any protected sectors or flash security. Flash security is disabled upon successful completion of the BE command. Attempts to issue a BE command while the BEDIS and FS fields are set results in the WEF flag being set in the EzPort status register. Also, this command is not accepted if the WEF or WIP field is set or if the WEN field is not set in the EzPort status register. 30.3.1.
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Command definition 30.3.1.11 Read FCCOB Registers at High Speed The Read FCCOB Registers at High Speed (FAST_RDFCCOB) command allows the user to read the contents of the flash common command object registers. After receiving the command, EzPort waits for one dummy byte of data before returning FCCOB register data starting at FCCOB 0 and ending with FCCOB B. This command can be run with an EzPort clock (EZP_CK) frequency half the internal system clock frequency of the microcontroller or slower.
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Chapter 30 EzPort Data continues being returned for as long as the EzPort chip select (EZP_CS) is asserted, with the address automatically incrementing. In this way, the entire contents of FlexRAM can be returned by one command. The initial address must be 32-bit aligned (the two LSBs must be zero). Attempts to read from an address which does not fall within the valid address range for the FlexRAM returns unknown data. See Flash memory map for EzPort access for more information.
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Flash memory map for EzPort access K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 700 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 31 Cyclic Redundancy Check (CRC) 31.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. The 16/32-bit code is calculated for 32 bits of data at a time. 31.1.
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Memory map and register descriptions 31.1.2 Block diagram The following is a block diagram of the CRC. TOT WAS Reverse Logic FXOR TOTR Seed MUX CRC Data Register [31:24] [23:16] [15:8] [7:0] NOT Logic CRC Data Reverse Logic Checksum CRC Polynomial Register [31:24] [23:16] [15:8] [7:0] CRC Data Register [31:24] [23:16] [15:8] [7:0] CRC Engine Data Combine Logic Polynomial 16-/32-bit Select TCRC Figure 31-1. Programmable cyclic redundancy check (CRC) block diagram 31.1.
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Chapter 31 Cyclic Redundancy Check (CRC) 31.2.1 CRC Data register (CRC_CRC) The CRC Data register contains the value of the seed, data, and checksum. When CTRL[WAS] is set, any write to the data register is regarded as the seed value. When CTRL[WAS] is cleared, any write to the data register is regarded as data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are not used for programming the seed value, and reads of these fields return an indeterminate value.
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Memory map and register descriptions 31.2.2 CRC Polynomial register (CRC_GPOLY) This register contains the value of the polynomial for the CRC calculation. The HIGH field contains the upper 16 bits of the CRC polynomial, which are used only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are used in both 16- and 32-bit CRC modes.
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Chapter 31 Cyclic Redundancy Check (CRC) CRC_CTRL field descriptions Field 31–30 TOT Description Type Of Transpose For Writes Define the transpose configuration of the data written to the CRC data register. See the description of the transpose feature for the available transpose options. 00 01 10 11 29–28 TOTR Type Of Transpose For Read Identify the transpose configuration of the value read from the CRC Data register. See the description of the transpose feature for the available transpose options.
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Functional description 31.3.1 CRC initialization/reinitialization To enable the CRC calculation, the user must program the WAS, POLYNOMIAL, and necessary parameters for transpose and CRC result inversion in the applicable registers. Asserting CTRL[WAS] enables the programming of the seed value into the CRC data register.
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Chapter 31 Cyclic Redundancy Check (CRC) 1. Set CTRL[TCRC] to enable 32-bit CRC mode. 2. Program the transpose and complement options in the CTRL register as required for the CRC calculation. See Transpose feature and CRC result complement for details. 3. Write a 32-bit polynomial to GPOLY[HIGH:LOW]. 4. Set CTRL[WAS] to program the seed value. 5. Write a 32-bit seed to CRC[HU:HL:LU:LL]. 6. Clear CTRL[WAS] to start writing data values. 7. Write data values into CRC[HU:HL:LU:LL].
PAGE 708
Functional description Bits in a byte are transposed, while bytes are not transposed. reg[31:0] becomes {reg[24:31], reg[16:23], reg[8:15], reg[0:7]} 31 24 23 16 15 24 31 16 23 8 8 7 0 15 0 7 Figure 31-5. Transpose type 01 3. CTRL[TOT] or CTRL[TOTR] is 10 Both bits in bytes and bytes are transposed. reg[31:0] becomes = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} 31 0 31 0 Figure 31-6. Transpose type 10 4.
PAGE 709
Chapter 31 Cyclic Redundancy Check (CRC) NOTE For 8-bit and 16-bit write accesses to the CRC data register, the data is transposed with zeros on the unused byte or bytes (taking 32 bits as a whole), but the CRC is calculated on the valid byte(s) only. When reading the CRC data register for a 16-bit CRC result and using transpose options 10 and 11, the resulting value after transposition resides in the CRC[HU:HL] fields.
PAGE 710
Functional description K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 710 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 711
Chapter 32 Analog-to-Digital Converter (ADC) 32.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The 16-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE For the chip specific modes of operation, see the power management information of the device. 32.1.
PAGE 712
Introduction • Configurable sample time and conversion speed/power • Conversion complete/hardware average complete flag and interrupt • Input clock selectable from up to four sources • Operation in Low-Power modes for lower noise • Asynchronous clock source for lower noise operation with option to output the clock • Selectable hardware conversion trigger with hardware channel select • Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value
PAGE 713
Chapter 32 Analog-to-Digital Converter (ADC) ADHWTSA SC1A Conversion trigger control ADHWTSn ADHWT SC1n ADTRG Control Registers (SC2, CFG1, CFG2) ADACKEN Interrupt MCU STOP AD23 TempP ADCK ADACK Clock divide Bus clock 2 ALTCLK abort transfer initialize PGA DADP0 DADP2 DADP3 AD4 convert VREF_OUT sample Control sequencer Async Clock Gen A D IC L K A D IV ADLPC/ADHSC MODE ADLSMP/ADLSTS DIFF ADCO trig g e r c o m p le te AIEN COCO ADCH C o m p a re tru e 1 A D V IN P PG, MG A
PAGE 714
ADC Signal Descriptions Table 32-1. ADC Signal Descriptions (continued) Signal DADM3–DADM0 Description I/O Differential Analog Channel Inputs I Single-Ended Analog Channel Inputs I VREFSH Voltage Reference Select High I VREFSL Voltage Reference Select Low I VDDA Analog Power Supply I VSSA Analog Ground I AD23–AD4 32.2.1 Analog Power (VDDA) The ADC analog portion uses VDDA as its power connection. In some packages, VDDA is connected internally to VDD.
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Chapter 32 Analog-to-Digital Converter (ADC) In some packages, VREFH is connected in the package to VDDA and VREFL to VSSA. If externally available, the positive reference(s) may be connected to the same potential as VDDA or may be driven by an external source to a level between the minimum Ref Voltage High and the VDDA potential. VREFH must never exceed VDDA. Connect the ground references to the same voltage potential as VSSA. 32.2.
PAGE 716
Register definition ADC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_B020 Status and Control Register 2 (ADC0_SC2) 32 R/W 0000_0000h 32.3.6/725 4003_B024 Status and Control Register 3 (ADC0_SC3) 32 R/W 0000_0000h 32.3.7/727 4003_B028 ADC Offset Correction Register (ADC0_OFS) 32 R/W 0000_0004h 32.3.8/729 4003_B02C ADC Plus-Side Gain Register (ADC0_PG) 32 R/W 0000_8200h 32.3.
PAGE 717
Chapter 32 Analog-to-Digital Converter (ADC) ADC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 400B_B01C Compare Value Registers (ADC1_CV2) 32 R/W 0000_0000h 32.3.5/724 400B_B020 Status and Control Register 2 (ADC1_SC2) 32 R/W 0000_0000h 32.3.6/725 400B_B024 Status and Control Register 3 (ADC1_SC3) 32 R/W 0000_0000h 32.3.7/727 400B_B028 ADC Offset Correction Register (ADC1_OFS) 32 R/W 0000_0004h 32.3.
PAGE 718
Register definition To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more then one status and control register: one for each conversion. The SC1B–SC1n registers indicate potentially multiple SC1 registers for use only in hardware trigger mode. See the chip configuration information about the number of SC1n registers specific to this device. The SC1n registers have identical fields, and are used in a "pingpong" approach to control ADC operation.
PAGE 719
Chapter 32 Analog-to-Digital Converter (ADC) ADCx_SC1n field descriptions Field 31–8 Reserved 7 COCO Description This field is reserved. This read-only field is reserved and always has the value 0. Conversion Complete Flag This is a read-only field that is set each time a conversion is completed when the compare function is disabled, or SC2[ACFE]=0 and the hardware average function is disabled, or SC3[AVGE]=0.
PAGE 720
Register definition ADCx_SC1n field descriptions (continued) Field Description 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 When DIFF=0, AD12 is selected as input ; when DIFF=1, it is reserved . When DIFF=0, AD13 is selected as input ; when DIFF=1, it is reserved . When DIFF=0, AD14 is selected as input ; when DIFF=1, it is reserved . When DIFF=0, AD15 is selected as input ; when DIFF=1, it is reserved .
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Chapter 32 Analog-to-Digital Converter (ADC) ADCx_CFG1 field descriptions Field 31–8 Reserved 7 ADLPC Description This field is reserved. This read-only field is reserved and always has the value 0. Low-Power Configuration Controls the power configuration of the successive approximation converter. This optimizes power consumption when higher sample rates are not required. 0 1 6–5 ADIV Clock Divide Select ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
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Register definition 32.3.3 ADC Configuration Register 2 (ADCx_CFG2) Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode.
PAGE 723
Chapter 32 Analog-to-Digital Converter (ADC) ADCx_CFG2 field descriptions (continued) Field Description 0 1 1–0 ADLSTS Normal conversion sequence selected. High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. Long Sample Time Select Selects between the extended sample times when long sample time is selected, that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs.
PAGE 724
Register definition Table 32-44.
PAGE 725
Chapter 32 Analog-to-Digital Converter (ADC) ADCx_CVn field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15–0 CV Compare Value. 32.3.6 Status and Control Register 2 (ADCx_SC2) The status and control register 2 (SC2) contains the conversion active, hardware/software trigger select, compare function, and voltage reference select of the ADC module.
PAGE 726
Register definition ADCx_SC2 field descriptions (continued) Field Description Indicates that a conversion or hardware averaging is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted. 0 1 6 ADTRG Conversion Trigger Select Selects the type of trigger used for initiating a conversion. Two types of trigger are selectable: • Software trigger: When software trigger is selected, a conversion is initiated following a write to SC1A.
PAGE 727
Chapter 32 Analog-to-Digital Converter (ADC) ADCx_SC2 field descriptions (continued) Field Description 10 11 Reserved Reserved 32.3.7 Status and Control Register 3 (ADCx_SC3) The Status and Control Register 3 (SC3) controls the calibration, continuous convert, and hardware averaging functions of the ADC module.
PAGE 728
Register definition ADCx_SC3 field descriptions (continued) Field Description calibration sequence. Once started, the calibration routine cannot be interrupted by writes to the ADC registers or the results will be invalid and CALF will set. Setting CAL will abort any current conversion. 6 CALF Calibration Failed Flag Displays the result of the calibration sequence.
PAGE 729
Chapter 32 Analog-to-Digital Converter (ADC) 32.3.8 ADC Offset Correction Register (ADCx_OFS) The ADC Offset Correction Register (OFS) contains the user-selected or calibrationgenerated offset error correction value. This register is a 2’s complement, left-justified, 16-bit value . The value in OFS is subtracted from the conversion and the result is transferred into the result registers, Rn.
PAGE 730
Register definition ADCx_PG field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15–0 PG Plus-Side Gain 32.3.10 ADC Minus-Side Gain Register (ADCx_MG) The Minus-Side Gain Register (MG) contains the gain error correction for the minus-side input in differential mode. This register is ignored in single-ended mode.
PAGE 731
Chapter 32 Analog-to-Digital Converter (ADC) Address: Base address + 34h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 CLPD W Reset 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 4 3 2 1 0 ADCx_CLPD field descriptions Field Description 31–6 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
PAGE 732
Register definition ADCx_CLP4 field descriptions Field Description 31–10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9–0 CLP4 Calibration Value 32.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3) For more information, see CLPD register description.
PAGE 733
Chapter 32 Analog-to-Digital Converter (ADC) 32.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1) For more information, see CLPD register description.
PAGE 734
Register definition 32.3.18 ADC PGA Register (ADCx_PGA) 31 30 29 28 27 26 25 24 23 0 R PGAEN Bit W 22 21 20 0 PGALPb Address: Base address + 50h offset 0 19 18 17 16 PGAG Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 ADCx_PGA field descriptions Field 31–24 Reserved 23 PGAEN Description This field is reserved.
PAGE 735
Chapter 32 Analog-to-Digital Converter (ADC) ADCx_PGA field descriptions (continued) Field Description 1010 1011 1100 1101 1110 1111 15–0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved This field is reserved. This read-only field is reserved and always has the value 0. 32.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMD) The Minus-Side General Calibration Value (CLMx) registers contain calibration information that is generated by the calibration function.
PAGE 736
Register definition 32.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLMS) For more information, see CLMD register description.
PAGE 737
Chapter 32 Analog-to-Digital Converter (ADC) 32.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM3) For more information, see CLMD register description.
PAGE 738
Functional description 32.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM1) For more information, see CLMD register description.
PAGE 739
Chapter 32 Analog-to-Digital Converter (ADC) initiated. When it is idle and the asynchronous clock output enable is disabled, or CFG2[ADACKEN]= 0, the module is in its lowest power state. The ADC can perform an analog-to-digital conversion on any of the software selectable channels. All modes perform conversion by a successive approximation algorithm. To meet accuracy specifications, the ADC module must be calibrated using the on-chip calibration function.
PAGE 740
Functional description 32.4.2 Clock select and divide control One of four clock sources can be selected as the clock source for the ADC module. This clock source is then divided by a configurable value to generate the input clock ADCK, to the module. The clock is selected from one of the following sources by means of CFG1[ADICLK]. • Bus clock. This is the default selection following reset. • Bus clock divided by two.
PAGE 741
Chapter 32 Analog-to-Digital Converter (ADC) selected using SC2[REFSEL]. The alternate (VALTH and VALTL) voltage reference pair may select additional external pins or internal sources depending on MCU configuration. See the chip configuration information on the voltage references specific to this MCU. 32.4.
PAGE 742
Functional description The conversion complete flag associated with the ADHWTSn received, that is, SC1n[COCO], is then set and an interrupt is generated if the respective conversion complete interrupt has been enabled, that is, SC1[AIEN]=1. 32.4.5 Conversion control Conversions can be performed as determined by CFG1[MODE] and SC1n[DIFF] as shown in the description of CFG1[MODE]. Conversions can be initiated by a software or hardware trigger.
PAGE 743
Chapter 32 Analog-to-Digital Converter (ADC) If continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion, by:. In software triggered operation, that is, when ADTRG=0, continuous conversions begin after SC1A is written and continue until aborted. In hardware triggered operation, that is, when ADTRG=1 and one ADHWTSn event has occurred, continuous conversions begin after a hardware trigger event and continue until aborted.
PAGE 744
Functional description • The MCU is reset or enters Low-Power Stop modes. • The MCU enters Normal Stop mode with ADACK not enabled. When a conversion is aborted, the contents of the data registers, Rn, are not altered. The data registers continue to be the values transferred after the completion of the last successful conversion. If the conversion was aborted by a reset or Low-Power Stop modes, RA and Rn return to their reset states. 32.4.5.
PAGE 745
Chapter 32 Analog-to-Digital Converter (ADC) The total conversion time depends upon: • The sample time as determined by CFG1[ADLSMP] and CFG2[ADLSTS] • The MCU bus frequency • The conversion mode, as determined by CFG1[MODE] and SC1n[DIFF] • The high speed configuration, that is, CFG2[ADHSC] • The frequency of the conversion clock, that is, fADCK. CFG2[ADHSC] is used to configure a higher clock input frequency. This will allow faster overall conversion times.
PAGE 746
Functional description Table 32-107. Single or first continuous time adder (SFCAdder) (continued) CFG1[AD LSMP] CFG2[AD ACKEN] CFG1[ADICLK] Single or first continuous time adder (SFCAdder) 0 0 11 5 μs + 5 ADCK cycles + 5 bus clock cycles 1. To achieve this time, CFG2[ADACKEN] must be 1 for at least 5 μs prior to the conversion is initiated. Table 32-108.
PAGE 747
Chapter 32 Analog-to-Digital Converter (ADC) Note The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications. 32.4.5.6 Conversion time examples The following examples use Figure 32-95 and the information provided in Table 32-107 through Table 32-111. 32.4.5.6.
PAGE 748
Functional description • Configured for longest adder • High-speed conversion disabled • Average enabled for 32 conversions The conversion time for this conversion is calculated by using Figure 32-95 and the information provided in Table 32-107 through Table 32-111. The following table lists the variables of the Figure 32-95. Table 32-113.
PAGE 749
Chapter 32 Analog-to-Digital Converter (ADC) The resulting conversion time is generated using the parameters listed in in the preceding table. Therefore, for bus clock and ADCK frequency equal to 20 MHz, the resulting conversion time is 1.45 µs. 32.4.5.7 Hardware average function The hardware average function can be enabled by setting SC3[AVGE]=1 to perform a hardware average of multiple conversions.
PAGE 750
Functional description Table 32-115. Compare modes SC2[AC FGT] SC2[AC REN] ADCCV1 relative to ADCCV2 0 0 1 Function Compare mode description — Less than threshold Compare true if the result is less than the CV1 registers. 0 — Greater than or equal to threshold Compare true if the result is greater than or equal to CV1 registers. 0 1 Less than or equal Outside range, not inclusive Compare true if the result is less than CV1 Or the result is greater than CV2.
PAGE 751
Chapter 32 Analog-to-Digital Converter (ADC) 32.4.7 Calibration function The ADC contains a self-calibration function that is required to achieve the specified accuracy. Calibration must be run, or valid calibration values written, after any reset and before a conversion is initiated. The calibration function sets the offset calibration value, the minus-side calibration values, and the plus-side calibration values.
PAGE 752
Functional description 2. Add the plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, and CLPS to the variable. 3. Divide the variable by two. 4. Set the MSB of the variable. 5. The previous two steps can be achieved by setting the carry bit, rotating to the right through the carry bit on the high byte and again on the low byte. 6. Store the value in the plus-side gain calibration register PG. 7. Repeat the procedure for the minus-side gain calibration value.
PAGE 753
Chapter 32 Analog-to-Digital Converter (ADC) OFS is automatically set according to calibration requirements once the self-calibration sequence is done, that is, SC3[CAL] is cleared. The user may write to OFS to override the calibration result if desired. If the OFS is written by the user to a value that is different from the calibration value, the ADC error specifications may not be met.
PAGE 754
Functional description For temperature calculations, use the VTEMP25 and temperature sensor slope values from the ADC Electricals table. In application code, the user reads the temperature sensor channel, calculates VTEMP, and compares to VTEMP25. If VTEMP is greater than VTEMP25 the cold slope value is applied in the preceding equation. If VTEMP is less than VTEMP25, the hot slope value is applied in the preceding equation. ADC Electricals table may only specify one temperature sensor slope value.
PAGE 755
Chapter 32 Analog-to-Digital Converter (ADC) 32.4.11.1 Normal Stop mode with ADACK disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the ADC in its Idle state. The contents of the ADC registers, including Rn, are unaffected by Normal Stop mode. After exiting from Normal Stop mode, a software or hardware trigger is required to resume conversions. 32.4.11.
PAGE 756
Initialization information 32.5 Initialization information This section gives an example that provides some basic direction on how to initialize and configure the ADC module. The user can configure the module for 16-bit, 12-bit, 10-bit, or 8-bit single-ended resolution or 16-bit, 13-bit, 11-bit, or 9-bit differential resolution, single or continuous conversion, and a polled or interrupt approach, among many other options.
PAGE 757
Chapter 32 Analog-to-Digital Converter (ADC) 6. Update the PGA register to enable or disable PGA and configure appropriate gain. This register is also used to select Power Mode and to check whether the module is chopper-stabilized. 32.5.1.2 Pseudo-code example In this example, the ADC module is set up with interrupts enabled to perform a single 10bit conversion at low-power with a long sample time on input channel 1, where ADCK is derived from the bus clock divided by 1.
PAGE 758
Application information Reset Initialize ADC CFG1 = 0x98 SC2 = 0x00 SC1n = 0x41 Check No SC1n[COCO]=1? Yes Read Rn to clear SC1n[COCO] Continue Figure 32-97. Initialization flowchart example 32.6 Application information The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an ADC. 32.6.1 External pins and routing 32.6.1.
PAGE 759
Chapter 32 Analog-to-Digital Converter (ADC) • VSSA is shared on the same pin as the MCU digital VSS. • VSSA and VDDA are shared with the MCU digital supply pins—In these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. If separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSA pin.
PAGE 760
Application information 32.6.1.3 Analog input pins The external analog inputs are typically shared with digital I/O pins on MCU devices. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. Use of 0.01 μF capacitors with good high-frequency characteristics is sufficient. These capacitors are not necessary in all cases, but when used, they must be placed as near as possible to the package pins and be referenced to VSSA.
PAGE 761
Chapter 32 Analog-to-Digital Converter (ADC) LSBERR = value of acceptable sampling error in LSBs N = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode or 16 in 16-bit mode Higher source resistances or higher-accuracy sampling is possible by setting CFG1[ADLSMP] and changing CFG2[ADLSTS] to increase the sample window, or decreasing ADCK frequency to increase sample time. 32.6.2.2 Pin leakage error Leakage on the I/O pins can cause conversion error if the external analog source resistance, RAS, is high.
PAGE 762
Application information There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in Wait or Normal Stop mode, or I/O activity cannot be halted, the following actions may reduce the effect of noise on the accuracy: • Place a 0.01 μF capacitor (CAS) on the selected input channel to VREFL or VSSA.
PAGE 763
Chapter 32 Analog-to-Digital Converter (ADC) 32.6.2.5 Linearity errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors, but the system designers must be aware of these errors because they affect overall accuracy: • Zero-scale error (EZS), sometimes called offset: This error is defined as the difference between the actual code width of the first conversion and the ideal code width.
PAGE 764
Application information • Non-monotonicity: Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. • Missing codes: Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 764 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 765
Chapter 33 Comparator (CMP) 33.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The comparator (CMP) module provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage, known as rail-to-rail operation. The Analog MUX (ANMUX) provides a circuit for selecting an analog input signal from eight channels.
PAGE 766
6-bit DAC key features • Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output • Selectable inversion on comparator output • Capability to produce a wide range of outputs such as: • Sampled • Windowed, which is ideal for certain PWM zero-crossing-detection applications • Digitally filtered: • Filter can be bypassed • Can be clocked via external SAMPLE signal or scaled bus clock • External hysteresis can be used at the same time that the output filter is
PAGE 767
Chapter 33 Comparator (CMP) 33.4 ANMUX key features • Two 8-to-1 channel mux • Operational over the entire supply range 33.5 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
PAGE 768
CMP block diagram VRSEL Vin1 Vin2 VOSEL[5:0] MUX DAC output MUX 64-level DACEN DAC PSEL[2:0] CMP MUX Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP Sample input CMP MUX ANMUX Window and filter control INM IRQ CMPO MSEL[2:0] Figure 33-1. CMP, DAC and ANMUX block diagram 33.6 CMP block diagram The following figure shows the block diagram for the CMP module. K20 Sub-Family Reference Manual, Rev. 1.
PAGE 769
Chapter 33 Comparator (CMP) Internal bus FILT_PER EN,PMODE,HYSCTRL[1:0] COS INV OPE WE FILTER_CNT SE COUT IER/F CFR/F INP + - CMPO Polarity select Window control Interrupt control Filter block INM IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock Clock prescaler FILT_PER 1 0 0 divided bus clock COUTA CGMUX SE 1 CMPO to PAD COS Figure 33-2.
PAGE 770
Memory map/register definitions • If enabled, the Filter block will incur up to one bus clock additional latency penalty on COUT due to the fact that COUT, which is crossing clock domain boundaries, must be resynchronized to the bus clock. • CR1[WE] and CR1[SE] are mutually exclusive. 33.7 Memory map/register definitions CMP memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_3000 CMP Control Register 0 (CMP0_CR0) 8 R/W 00h 33.7.
PAGE 771
Chapter 33 Comparator (CMP) CMPx_CR0 field descriptions Field 7 Reserved 6–4 FILTER_CNT Description This field is reserved. This read-only field is reserved and always has the value 0. Filter Sample Count Represents the number of consecutive samples that must agree prior to the comparator ouput filter accepting a new output state. For information regarding filter programming and latency, see the CMP functional description. 000 001 010 011 100 101 110 111 Filter is disabled.
PAGE 772
Memory map/register definitions CMPx_CR1 field descriptions (continued) Field Description 0 1 6 WE Windowing Enable At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is set and WE is cleared. However, avoid writing 1s to both field locations because this "11" case is reserved and may change in future implementations. 0 1 5 Reserved 4 PMODE Windowing mode is not selected. Windowing mode is selected. This field is reserved.
PAGE 773
Chapter 33 Comparator (CMP) 33.7.3 CMP Filter Period Register (CMPx_FPR) Address: Base address + 2h offset Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 FILT_PER 0 0 0 0 CMPx_FPR field descriptions Field 7–0 FILT_PER Description Filter Sample Period Specifies the sampling period, in bus clock cycles, of the comparator output filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter programming and latency details appear in the CMP functional description.
PAGE 774
Memory map/register definitions CMPx_SCR field descriptions (continued) Field Description 0 1 3 IEF Comparator Interrupt Enable Falling Enables the CFF interrupt from the CMP. When this field is set, an interrupt will be asserted when CFF is set. 0 1 2 CFR Detects a rising-edge on COUT, when set, during normal operation. CFR is cleared by writing 1 to it. During Stop modes, CFR is level sensitive . Rising-edge on COUT has not been detected. Rising-edge on COUT has occurred.
PAGE 775
Chapter 33 Comparator (CMP) CMPx_DACCR field descriptions (continued) Field Description 0 1 5–0 VOSEL V is selected as resistor ladder network supply reference V. in1in V is selected as resistor ladder network supply reference V. in2in DAC Output Voltage Select Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in . 33.7.
PAGE 776
CMP functional description CMPx_MUXCR field descriptions (continued) Field Description NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator. 000 001 010 011 100 101 110 111 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 33.8 CMP functional description The CMP module can be used to compare two analog input voltages applied to INP and INM.
PAGE 777
Chapter 33 Comparator (CMP) The "windowing mode" is enabled by setting CR1[WE]. When set, the comparator output is sampled only when WINDOW=1. This feature can be used to ignore the comparator output during time periods in which the input voltages are not valid. This is especially useful when implementing zero-crossing-detection for certain PWM applications. The comparator filter and sampling features can be combined as shown in the following table. Individual modes are discussed below. Table 33-29.
PAGE 778
CMP functional description For cases where a comparator is used to drive a fault input, for example, for a motorcontrol module such as FTM, it must be configured to operate in Continuous mode so that an external fault can immediately pass through the comparator to the target fault circuitry. Note Filtering and sampling settings must be changed only after setting CR1[SE]=0 and CR0[FILTER_CNT]=0x00. This resets the filter to a known state. 33.8.1.
PAGE 779
Chapter 33 Comparator (CMP) NOTE See the chip configuration section for the source of sample/ window input. The analog comparator block is powered and active. CMPO may be optionally inverted, but is not subject to external sampling or filtering. Both window control and filter blocks are completely bypassed. SCR[COUT] is updated continuously. The path from comparator input pins to output pin is operating in combinational unclocked mode. COUT and COUTA are identical.
PAGE 780
CMP functional description The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Non-Filtered (# 3B) is in how the clock to the filter block is derived. In #3A, the clock to filter block is externally derived while in #3B, the clock to filter block is internally derived. The comparator filter has no other function than sample/hold of the comparator output in this mode (# 3B).
PAGE 781
Chapter 33 Comparator (CMP) Internal bus EN, PMODE, HYSTCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT > 0x01 0 INP + - CMPO Polarity select Window control IER/F CFR/F 1 Interrupt control Filter block INM IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock FILT_PER Clock prescaler 1 0 0 divided bus clock COUTA CGMUX SE=1 1 CMPO to PAD COS Figure 33-30. Sampled, Filtered (# 4A): sampling point externally driven K20 Sub-Family Reference Manual, Rev. 1.
PAGE 782
CMP functional description Internal bus OPE FILT_PER EN, PMODE,HYSTCTR[1:0] COS INV WE FILTER_CNT SE COUT IER/F CFR/F >0x01 0 1 INP + - Polarity CMPO select Window control Filter block Interrupt control INM IRQ COUT WINDOW/SAMPLE bus clock FILT_PER Clock prescaler To other SOC functions 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 33-31.
PAGE 783
Chapter 33 Comparator (CMP) WI NDOW Plus input Minus input CMPO COUTA Figure 33-32. Windowed mode operation Internal bus EN, PMODE,HYSCTR[1:0] FILT_PER INV COS OPE WE FILTER_CNT SE COUT 0x01 IER/F CFR/F 0 INP + - CMPO Polarity select Window control Interrupt control Filter block INM IRQ COUT To other SOC functions WINDOW/SAMPLE bus clock FILT_PER Clock prescaler 1 0 0 divided bus clock COUTA CGMUX SE=0 1 CMPO to PAD COS Figure 33-33.
PAGE 784
CMP functional description When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. 33.8.1.6 Windowed/Resampled mode (# 6) The following figure uses the same input stimulus shown in Figure 33-32, and adds resampling of COUTA to generate COUT. Samples are taken at the time points indicated by the arrows in the figure. Again, prop delays and latency are ignored for the sake of clarity.
PAGE 785
Chapter 33 Comparator (CMP) 33.8.1.7 Windowed/Filtered mode (#7) This is the most complex mode of operation for the comparator block, as it uses both windowing and filtering features. It also has the highest latency of any of the modes. This can be approximated: up to 1 bus clock synchronization in the window function + ((CR0[FILTER_CNT] * FPR[FILT_PER]) + 1) * bus clock for the filter function. When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1.
PAGE 786
CMP functional description 33.8.2.2 Stop mode operation Subject to platform-specific clock restrictions, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin.
PAGE 787
Chapter 33 Comparator (CMP) During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] to reflect an input change or a configuration change to one of the components involved in the data path. When programmed for filtering modes, COUT will initially be equal to 0, until sufficient clock cycles have elapsed to fill all stages of the filter. This occurs even if COUTA is at a logic 1. 33.8.
PAGE 788
CMP functional description Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. Note Always switch to this setting prior to making any changes in filter parameters. This resets the filter to a known state. Switching CR0[FILTER_CNT] on the fly without this intermediate step can result in unexpected behavior. If CR1[SE]=1, the filter takes samples of COUTA on each positive transition of the sample input.
PAGE 789
Chapter 33 Comparator (CMP) Table 33-30.
PAGE 790
Digital-to-analog converter block diagram 33.11 Digital-to-analog converter block diagram The following figure shows the block diagram of the DAC module. It contains a 64-tap resistor ladder network and a 64-to-1 multiplexer, which selects an output voltage from one of 64 distinct levels that outputs from DACO. It is controlled through the DAC Control Register (DACCR). Its supply reference source can be selected from two sources Vin1 and Vin2. The module can be powered down or disabled when not in use.
PAGE 791
Chapter 33 Comparator (CMP) 33.13 DAC resets This module has a single reset input, corresponding to the chip-wide peripheral reset. 33.14 DAC clocks This module has a single clock input, the bus clock. 33.15 DAC interrupts This module has no interrupts. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
PAGE 792
DAC interrupts K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 792 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 793
Chapter 34 12-bit Digital-to-Analog Converter (DAC) 34.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The 12-bit digital-to-analog converter (DAC) is a low-power general-purpose DAC. The output of this DAC can be placed on an external pin or set as one of the inputs to the analog comparator, operational amplifiers (OPAMPs), analog-to-digital converter (ADC), or other peripherals. 34.
PAGE 794
Memory map/register definition DACREF_1 DACREF_2 DACRFS MUX AMP buffer Vin DACEN MUX 4096-level VDD - LPEN Vo Vout + DACDAT[11:0] 12 Hardware trigger DACBFWMF DACSWTRG DACBFWM DACBFEN DACBFUP DACBFRP Data Buffer DACBWIEN & DACBFRPTF DACBTIEN & OR dac_interrupt DACBFRPBF DACBBIEN & DACBFMD DACTRGSE Figure 34-1. DAC block diagram 34.
PAGE 795
Chapter 34 12-bit Digital-to-Analog Converter (DAC) NOTE The below memory map describes 2 DACs (DAC0 and DAC1) map. The address of a register is the sum of a base address and an address offset. The base address is defined at the chip level. The address offset is defined at the module level. DAC memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 400C_C000 DAC Data Low Register (DAC0_DAT0L) 8 R/W 00h 34.4.
PAGE 796
Memory map/register definition DACx_DATnL field descriptions Field 7–0 DATA[7:0] Description When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula: Vout = Vin * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA is mapped to the 16-word buffer. 34.4.
PAGE 797
Chapter 34 12-bit Digital-to-Analog Converter (DAC) DACx_SR field descriptions (continued) Field Description 0 1 The DAC buffer read pointer has not reached the watermark level. The DAC buffer read pointer has reached the watermark level. 1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag 0 DACBFRPBF DAC Buffer Read Pointer Bottom Position Flag 0 1 0 1 The DAC buffer read pointer is not zero. The DAC buffer read pointer is zero. The DAC buffer read pointer is not equal to C2[DACBFUP].
PAGE 798
Memory map/register definition DACx_C0 field descriptions (continued) Field Description NOTE: See the 12-bit DAC electrical characteristics of the device data sheet for details on the impact of the modes below. 0 1 High-Power mode Low-Power mode 2 DACBWIEN DAC Buffer Watermark Interrupt Enable 1 DACBTIEN DAC Buffer Read Pointer Top Flag Interrupt Enable 0 DACBBIEN DAC Buffer Read Pointer Bottom Flag Interrupt Enable 0 1 0 1 0 1 The DAC buffer watermark interrupt is disabled.
PAGE 799
Chapter 34 12-bit Digital-to-Analog Converter (DAC) DACx_C1 field descriptions (continued) Field Description 2–1 DACBFMD DAC Buffer Work Mode Select 0 DACBFEN DAC Buffer Enable 00 01 01 10 11 0 1 Normal mode Swing mode Reserved One-Time Scan mode Reserved Buffer read pointer is disabled. The converted data is always the first word of the buffer. Buffer read pointer is enabled. The converted data is the word that the read pointer points to.
PAGE 800
Functional description 34.5.1 DAC data buffer operation When the DAC is enabled and the buffer is not enabled, the DAC module always converts the data in DAT0 to analog output voltage. When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage. The data buffer read pointer advances to the next word whenever any hardware or software trigger event occurs. Refer to Introduction for the hardware trigger connection.
PAGE 801
Chapter 34 12-bit Digital-to-Analog Converter (DAC) Table 34-47. Modes of DAC data buffer operation (continued) Modes Description Buffer One-time Scan mode The read pointer increases by 1 every time the trigger occurs. When it reaches the upper limit, it stops there. If read pointer is reset to the address other than the upper limit, it will increase to the upper address and stop there again. NOTE: If the software set the read pointer to the upper limit, the read pointer will not advance in this mode.
PAGE 802
Functional description K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 802 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 803
Chapter 35 Voltage Reference (VREFV1) 35.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Voltage Reference(VREF) is intended to supply an accurate voltage output that can be trimmed in 0.5 mV steps. The VREF can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC, DAC, or CMP.
PAGE 804
Introduction 6 BITS 1.75 V Regulator TRM SC[VREFEN] SC[MODE_LV] 1.75 V 2 BITS SC[VREFST] BANDGAP VDDA DEDICATED OUTPUT PIN VREF_OUT 100nF REGULATION BUFFER Figure 35-1. Voltage reference block diagram 35.1.1 Overview The Voltage Reference provides a buffered reference voltage for use as an external reference. In addition, the buffered reference is available internally for use with on chip peripherals such as ADCs and DACs. Refer to the chip configuration chapter for a description of these options.
PAGE 805
Chapter 35 Voltage Reference (VREFV1) • Bandgap enabled/standby (output buffer disabled) • Low power buffer mode (output buffer enabled) • High power buffer mode (output buffer enabled) • 1.2 V output at room temperature • Dedicated output pin, VREF_OUT 35.1.3 Modes of Operation The Voltage Reference continues normal operation in Run, Wait, and Stop modes. The Voltage Reference can also run in Very Low Power Run (VLPR), Very Low Power Wait (VLPW) and Very Low Power Stop (VLPS).
PAGE 806
Memory Map and Register Definition 35.2 Memory Map and Register Definition VREF memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_4000 VREF Trim Register (VREF_TRM) 8 R/W See section 35.2.1/806 4007_4001 VREF Status and Control Register (VREF_SC) 8 R/W 00h 35.2.2/807 35.2.1 VREF Trim Register (VREF_TRM) This register contains bits that contain the trim data for the Voltage Reference.
PAGE 807
Chapter 35 Voltage Reference (VREFV1) 35.2.2 VREF Status and Control Register (VREF_SC) This register contains the control bits used to enable the internal voltage reference and to select the buffer mode to be used.
PAGE 808
Functional Description VREF_SC field descriptions (continued) Field Description This bit indicates that the bandgap reference within the Voltage Reference module has completed its startup and stabilization. 0 1 1–0 MODE_LV The module is disabled or not stable. The module is stable. Buffer Mode selection These bits select the buffer modes for the Voltage Reference module.
PAGE 809
Chapter 35 Voltage Reference (VREFV1) 35.3.2 Voltage Reference Enabled, SC[VREFEN] = 1 When SC[VREFEN] = 1, the Voltage Reference is enabled, and different modes should be set by the SC[MODE_LV] bits. 35.3.2.1 SC[MODE_LV]=00 The internal VREF bandgap is enabled to generate an accurate 1.2 V output that can be trimmed with the TRM register's TRIM[5:0] bitfield. The bandgap requires some time for startup and stabilization.
PAGE 810
Initialization/Application Information If this mode is entered from the standby mode (SC[MODE_LV] = 00, SC[VREFEN] = 1) there will be a delay before the buffer output is settled at the final value. This is the buffer start up delay (Tstup) and the value is specified in the appropriate device data sheet. If this mode is entered when the VREF module is enabled then you must wait the longer of Tstup or until SC[VREFST] = 1.
PAGE 811
Chapter 36 Programmable Delay Block (PDB) 36.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Programmable Delay Block (PDB) provides controllable delays from either an internal or an external trigger, or a programmable interval tick, to the hardware trigger inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing between ADC conversions and/or DAC updates can be achieved.
PAGE 812
Introduction • Optional back-to-back mode operation, which enables the ADC conversions complete to trigger the next PDB channel • One programmable delay interrupt • One sequence error interrupt • One channel flag and one sequence error flag per pre-trigger • DMA support • Up to eight DAC interval triggers • One interval trigger output per DAC • One 16-bit delay interval register per DAC trigger output • Optional bypass of the delay interval trigger registers • Optional external triggers • Up to eight pulse
PAGE 813
Chapter 36 Programmable Delay Block (PDB) • Y — Total number of Pulse-Out's. • y — Pulse-Out number, valid value is from 0 to Y-1. NOTE The number of module output triggers to core is chip-specific. For module to core output triggers implementation, see the chip configuration information. 36.1.3 Back-to-back acknowledgment connections PDB back-to-back operation acknowledgment connections are chip-specific. For implementation, see the chip configuration information. 36.1.
PAGE 814
Introduction Ack 0 PDBCHnDLY0 = Pre-trigger 0 BB[0], TOS[0] Ch n pre-trigger 0 EN[0] Ack m PDBCHnDLYm = Pre-trigger m BB[m], TOS[m] Ch n pre-trigger m EN[m] Sequence Error Detection ERR[M - 1:0] Ch n trigger PDBMOD PDBCNT = PDB Counter Control Logic DACINTx CONT DAC interval trigger x = DAC Interval Counter x TOEx MULT EXTx DAC ext trigger input x PRESCALER DAC interval trigger x Trigger-In 0 Trigger-In 1 POyDLY1 Trigger-In 14 = SWTRIG POyDLY2 TRIGSEL Pulse Generation = P
PAGE 815
Chapter 36 Programmable Delay Block (PDB) 36.1.6 Modes of operation PDB ADC trigger operates in the following modes. Disabled: Counter is off, all pre-trigger and trigger outputs are low if PDB is not in backto-back operation of Bypass mode. Debug: Counter is paused when processor is in Debug mode, and the counter for dac trigger is also paused in Debug mode.
PAGE 816
Memory map and register definition PDB memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_6000 Status and Control Register (PDB0_SC) 32 R/W 0000_0000h 36.3.1/817 4003_6004 Modulus Register (PDB0_MOD) 32 R/W 0000_FFFFh 36.3.2/819 4003_6008 Counter Register (PDB0_CNT) 32 R 0000_0000h 36.3.3/820 4003_600C Interrupt Delay Register (PDB0_IDLY) 32 R/W 0000_FFFFh 36.3.
PAGE 817
Chapter 36 Programmable Delay Block (PDB) 36.3.
PAGE 818
Memory map and register definition PDBx_SC field descriptions (continued) Field Description 0 1 PDB sequence error interrupt disabled. PDB sequence error interrupt enabled. 16 SWTRIG Software Trigger 15 DMAEN DMA Enable When PDB is enabled and the software trigger is selected as the trigger input source, writing 1 to this bit reset and restarts the counter. Writing 0 to this bit has no effect. Reading this bit results 0.
PAGE 819
Chapter 36 Programmable Delay Block (PDB) PDBx_SC field descriptions (continued) Field Description 7 PDBEN PDB Enable 6 PDBIF PDB Interrupt Flag 5 PDBIE PDB Interrupt Enable. 0 1 PDB disabled. Counter is off. PDB enabled. This bit is set when the counter value is equal to the IDLY register. Writing zero clears this bit. Enables the PDB interrupt. When this bit is set and DMAEN is cleared, PDBIF generates a PDB interrupt.
PAGE 820
Memory map and register definition PDBx_MOD field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15–0 MOD PDB Modulus Specifies the period of the counter. When the counter reaches this value, it will be reset back to zero. If the PDB is in Continuous mode, the count begins anew. Reading these bits returns the value of internal register that is effective for the current cycle of PDB. 36.3.
PAGE 821
Chapter 36 Programmable Delay Block (PDB) PDBx_IDLY field descriptions (continued) Field Description equal to the IDLY. Reading these bits returns the value of internal register that is effective for the current cycle of the PDB. 36.3.5 Channel n Control Register 1 (PDBx_CHnC1) Each PDB channel has one Control Register, CHnC1. The bits in this register control the functionality of each PDB channel operation.
PAGE 822
Memory map and register definition 36.3.6 Channel n Status Register (PDBx_CHnS) Address: 4003_6000h base + 14h offset + (40d × i), where i=0d to 1d Bit 31 30 29 28 27 26 25 24 23 22 21 0 R 0 0 0 0 19 18 17 16 15 14 13 12 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 0 CF W Reset 20 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 ERR 0 0 0 0 0 0 0 0 0 PDBx_CHnS field descriptions Field Description 31–24 Reserved This field is reserved.
PAGE 823
Chapter 36 Programmable Delay Block (PDB) 36.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1) Address: 4003_6000h base + 1Ch offset + (40d × i), where i=0d to 1d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 0 R 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DLY W Reset 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDBx_CHnDLY1 field descriptions Field Description 31–16 Reserved This field is reserved.
PAGE 824
Memory map and register definition PDBx_DACINTCn field descriptions (continued) Field Description 0 TOE DAC Interval Trigger Enable This bit enables the DAC interval trigger. 0 1 DAC interval trigger disabled. DAC interval trigger enabled. 36.3.
PAGE 825
Chapter 36 Programmable Delay Block (PDB) PDBx_POEN field descriptions (continued) Field Description 0 1 PDB Pulse-Out disabled PDB Pulse-Out enabled 36.3.
PAGE 826
Functional description • Trigger input event to pre-trigger m = (prescaler X multiplication factor X delay m) + 2 peripheral clock cycles • Add one additional peripheral clock cycle to determine the time at which the channel trigger output change. Each channel is associated with one ADC block. PDB channel n pre-trigger outputs 0 to M and trigger output is connected to ADC hardware trigger select and hardware trigger inputs.
PAGE 827
Chapter 36 Programmable Delay Block (PDB) When an ADC conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress and ADCnSC1[COCO] is not set, a new trigger from PDB channel n pre-trigger m cannot be accepted by ADCn. Therefore every time when one PDB channel n pre-trigger and trigger output starts an ADC conversion, an internal lock associated with the corresponding pre-trigger is activated.
PAGE 828
Functional description DAC interval counters are also reset when the PDB counter reaches the MOD register value; therefore, when the PDB counter rolls over to zero, the DAC interval counters starts anew. Together, the DAC interval trigger pulse and the ADC pre-trigger/trigger pulses allow precise timing of DAC updates and ADC measurements. This is outlined in the typical use case described in the following diagram.
PAGE 829
Chapter 36 Programmable Delay Block (PDB) The pulse-out connections implemented in this MCU are described in the device's chip configuration details. 36.4.5 Updating the delay registers The following registers control the timing of the PDB operation; and in some of the applications, they may need to become effective at the same time.
PAGE 830
Functional description CHnDLY1 CHnDLY0 PDB Counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 36-54. Registers Update with SC[LDMOD] = 00 CHnDLY1 CHnDLY0 PDB Counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 36-55. Registers update with SC[LDMOD] = x1 36.4.6 Interrupts PDB can generate two interrupts: PDB interrupt and PDB sequence error interrupt. The following table summarizes the interrupts. Table 36-55.
PAGE 831
Chapter 36 Programmable Delay Block (PDB) 36.5 Application information 36.5.1 Impact of using the prescaler and multiplication factor on timing resolution Use of prescaler and multiplication factor greater than 1 limits the count/delay accuracy in terms of peripheral clock cycles (to the modulus of the prescaler X multiplication factor).
PAGE 832
Application information K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 832 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 833
Chapter 37 FlexTimer Module (FTM) 37.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The FlexTimer module (FTM) is a two-to-eight channel timer that supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The FTM time reference is a 16-bit counter that can be used as an unsigned or signed counter. 37.1.
PAGE 834
Introduction Motor control and power conversion features have been added through a dedicated set of registers and defaults turn off all new features. The new features, such as hardware deadtime insertion, polarity, fault control, and output forcing and masking, greatly reduce loading on the execution software and are usually each controlled by a group of registers. FlexTimer input triggers can be from comparators, ADC, or other submodules to initiate timer functions automatically.
PAGE 835
Chapter 37 FlexTimer Module (FTM) • The capture can occur on rising edges, falling edges or both edges • An input filter can be selected for some channels • In Output Compare mode the output signal can be set, cleared, or toggled on match • All channels can be configured for center-aligned PWM mode • Each pair of channels can be combined to generate a PWM signal with independent control of both edges of PWM signal • The FTM channels can operate as pairs with equal outputs, pairs with complementary outputs,
PAGE 836
Introduction real time reference or provide the interrupt sources needed to wake the MCU from Wait mode, the power can then be saved by disabling FTM functions before entering Wait mode. 37.1.4 Block diagram The FTM uses one input/output (I/O) pin per channel, CHn (FTM channel (n)) where n is the channel number (0–7). The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable initial and final values and its counting can be up or up-down.
PAGE 837
Chapter 37 FlexTimer Module (FTM) CLKS FTMEN QUADEN no clock selected (FTM counter disable) system clock fixed frequency clock external clock phase A phase B PS prescaler (1, 2, 4, 8, 16, 32, 64 or 128) synchronizer Quadrature decoder QUADEN CPWMS CAPTEST INITTRIGEN CNTIN FAULTM[1:0] FFVAL[3:0] FAULTIE FAULTnEN* FFLTRnEN* FTM counter FAULTIN FAULTF FAULTFn* fault control fault input n* CH0IE CH0F input capture mode logic C0V input capture mode logic C1V DECAPEN COMBINE0 CPWMS MS1B:MS1A ELS1B
PAGE 838
FTM signal descriptions 37.2 FTM signal descriptions Table 37-1 shows the user-accessible signals for the FTM. Table 37-1. FTM signal descriptions Signal Description I/O Function EXTCLK External clock. FTM external clock can be selected to drive the FTM counter. I The external clock input signal is used as the FTM counter clock if selected by CLKS[1:0] bits in the SC register. This clock signal must not exceed 1/4 of system clock frequency.
PAGE 839
Chapter 37 FlexTimer Module (FTM) The second set has the FTM specific registers. Any second set registers, or bits within these registers, that are used by an unavailable function in the FTM configuration remain in the memory map and in the reset value, so they have no active function. Note Do not write to the FTM specific registers (second set registers) when FTMEN = 0. 37.3.2 Register descriptions Accesses to reserved addresses result in transfer errors.
PAGE 840
Memory map and register definition FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_8058 Synchronization (FTM0_SYNC) 32 R/W 0000_0000h 37.3.11/ 854 4003_805C Initial State For Channels Output (FTM0_OUTINIT) 32 R/W 0000_0000h 37.3.12/ 857 4003_8060 Output Mask (FTM0_OUTMASK) 32 R/W 0000_0000h 37.3.13/ 858 4003_8064 Function For Linked Channels (FTM0_COMBINE) 32 R/W 0000_0000h 37.3.
PAGE 841
Chapter 37 FlexTimer Module (FTM) FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_9024 Channel (n) Status And Control (FTM1_C3SC) 32 R/W 0000_0000h 37.3.6/847 4003_9028 Channel (n) Value (FTM1_C3V) 32 R/W 0000_0000h 37.3.7/849 4003_902C Channel (n) Status And Control (FTM1_C4SC) 32 R/W 0000_0000h 37.3.6/847 4003_9030 Channel (n) Value (FTM1_C4V) 32 R/W 0000_0000h 37.3.
PAGE 842
Memory map and register definition FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4003_9090 FTM Inverting Control (FTM1_INVCTRL) 32 R/W 0000_0000h 37.3.25/ 882 4003_9094 FTM Software Output Control (FTM1_SWOCTRL) 32 R/W 0000_0000h 37.3.26/ 883 4003_9098 FTM PWM Load (FTM1_PWMLOAD) 32 R/W 0000_0000h 37.3.27/ 885 400B_8000 Status And Control (FTM2_SC) 32 R/W 0000_0000h 37.3.
PAGE 843
Chapter 37 FlexTimer Module (FTM) FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 400B_8070 Channels Polarity (FTM2_POL) 32 R/W 0000_0000h 37.3.17/ 867 400B_8074 Fault Mode Status (FTM2_FMS) 32 R/W 0000_0000h 37.3.18/ 870 400B_8078 Input Capture Filter Control (FTM2_FILTER) 32 R/W 0000_0000h 37.3.19/ 872 400B_807C Fault Control (FTM2_FLTCTRL) 32 R/W 0000_0000h 37.3.
PAGE 844
Memory map and register definition 37.3.3 Status And Control (FTMx_SC) SC contains the overflow status flag and control bits used to configure the interrupt enable, FTM configuration, clock source, and prescaler factor. These controls relate to all channels within this module.
PAGE 845
Chapter 37 FlexTimer Module (FTM) FTMx_SC field descriptions (continued) Field 6 TOIE Description Timer Overflow Interrupt Enable Enables FTM overflow interrupts. 0 1 5 CPWMS Disable TOF interrupts. Use software polling. Enable TOF interrupts. An interrupt is generated when TOF equals one. Center-Aligned PWM Select Selects CPWM mode. This mode configures the FTM to operate in Up-Down Counting mode. This field is write protected. It can be written only when MODE[WPDIS] = 1.
PAGE 846
Memory map and register definition Address: Base address + 4h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 COUNT W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_CNT field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15–0 COUNT Counter Value 37.3.
PAGE 847
Chapter 37 FlexTimer Module (FTM) 37.3.6 Channel (n) Status And Control (FTMx_CnSC) CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. Table 37-67.
PAGE 848
Memory map and register definition Table 37-67. Mode, edge, and level selection (continued) DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration 1 0 0 X0 See the following table (Table 37-8). Dual Edge Capture One-Shot Capture mode X1 Continuous Capture mode Table 37-68.
PAGE 849
Chapter 37 FlexTimer Module (FTM) FTMx_CnSC field descriptions (continued) Field Description 0 1 5 MSB Disable channel interrupts. Use software polling. Enable channel interrupts. Channel Mode Select Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See Table 37-7. This field is write protected. It can be written only when MODE[WPDIS] = 1. 4 MSA Channel Mode Select Used for further selections in the channel logic.
PAGE 850
Memory map and register definition Address: Base address + 10h offset + (8d × i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 VAL W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_CnV field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
PAGE 851
Chapter 37 FlexTimer Module (FTM) Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be checked using only one read of STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to STATUS. Hardware sets the individual channel flags when an event occurs on the channel. CHF is cleared by reading STATUS while CHnF is set and then writing a 0 to the CHF bit. Writing a 1 to CHF has no effect.
PAGE 852
Memory map and register definition FTMx_STATUS field descriptions (continued) Field Description 0 1 6 CH6F Channel 6 Flag See the register description. 0 1 5 CH5F See the register description. See the register description. See the register description. See the register description. No channel event has occurred. A channel event has occurred. Channel 1 Flag See the register description. 0 1 0 CH0F No channel event has occurred. A channel event has occurred.
PAGE 853
Chapter 37 FlexTimer Module (FTM) • • • • • Fault control mode and interrupt Capture Test mode PWM synchronization Write protection Channel output initialization These controls relate to all channels within this module.
PAGE 854
Memory map and register definition FTMx_MODE field descriptions (continued) Field Description 0 1 3 PWMSYNC PWM Synchronization Mode Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. See PWM synchronization. The PWMSYNC bit configures the synchronization when SYNCMODE is zero. 0 1 2 WPDIS No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
PAGE 855
Chapter 37 FlexTimer Module (FTM) NOTE The software trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a potential conflict if used together when SYNCMODE = 0. Use only hardware or software triggers but not both at the same time, otherwise unpredictable behavior is likely to happen. The selection of the loading point, CNTMAX and CNTMIN bits, is intended to provide the update of MOD, CNTIN, and CnV registers across all enabled channels simultaneously.
PAGE 856
Memory map and register definition FTMx_SYNC field descriptions (continued) Field Description Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2 happens when a rising edge is detected at the trigger 2 input signal. 0 1 5 TRIG1 PWM Synchronization Hardware Trigger 1 Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1 happens when a rising edge is detected at the trigger 1 input signal. 0 1 4 TRIG0 Enables hardware trigger 0 to the PWM synchronization.
PAGE 857
Chapter 37 FlexTimer Module (FTM) 37.3.
PAGE 858
Memory map and register definition FTMx_OUTINIT field descriptions (continued) Field Description 0 1 2 CH2OI The initialization value is 0. The initialization value is 1. Channel 2 Output Initialization Value Selects the value that is forced into the channel output when the initialization occurs. 0 1 1 CH1OI The initialization value is 0. The initialization value is 1. Channel 1 Output Initialization Value Selects the value that is forced into the channel output when the initialization occurs.
PAGE 859
Chapter 37 FlexTimer Module (FTM) FTMx_OUTMASK field descriptions Field 31–8 Reserved 7 CH7OM Description This field is reserved. This read-only field is reserved and always has the value 0. Channel 7 Output Mask Defines if the channel output is masked or unmasked. 0 1 6 CH6OM Channel 6 Output Mask Defines if the channel output is masked or unmasked. 0 1 5 CH5OM Defines if the channel output is masked or unmasked. Defines if the channel output is masked or unmasked.
PAGE 860
Memory map and register definition 37.3.14 Function For Linked Channels (FTMx_COMBINE) This register contains the control bits used to configure the fault control, synchronization, deadtime insertion, Dual Edge Capture mode, Complementary, and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2, 4, and 6.
PAGE 861
Chapter 37 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field 27 DECAP3 Description Dual Edge Capture Mode Captures For n = 6 Enables the capture of the FTM counter value according to the channel (n) input event and the configuration of the dual edge capture bits. This field applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and when the capture of channel (n+1) event is made.
PAGE 862
Memory map and register definition FTMx_COMBINE field descriptions (continued) Field 20 DTEN2 Description Deadtime Enable For n = 4 Enables the deadtime insertion in the channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 19 DECAP2 The deadtime insertion in this pair of channels is disabled. The deadtime insertion in this pair of channels is enabled.
PAGE 863
Chapter 37 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field Description 0 1 13 SYNCEN1 Synchronization Enable For n = 2 Enables PWM synchronization of registers C(n)V and C(n+1)V. 0 1 12 DTEN1 The fault control in this pair of channels is disabled. The fault control in this pair of channels is enabled. The PWM synchronization in this pair of channels is disabled. The PWM synchronization in this pair of channels is enabled.
PAGE 864
Memory map and register definition FTMx_COMBINE field descriptions (continued) Field 7 Reserved 6 FAULTEN0 Description This field is reserved. This read-only field is reserved and always has the value 0. Fault Control Enable For n = 0 Enables the fault control in channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 5 SYNCEN0 Synchronization Enable For n = 0 Enables PWM synchronization of registers C(n)V and C(n+1)V.
PAGE 865
Chapter 37 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field Description 0 COMBINE0 Combine Channels For n = 0 Enables the combine feature for channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 Channels (n) and (n+1) are independent. Channels (n) and (n+1) are combined. 37.3.15 Deadtime Insertion Control (FTMx_DEADTIME) This register selects the deadtime prescaler factor and deadtime value.
PAGE 866
Memory map and register definition 37.3.16 FTM External Trigger (FTMx_EXTTRIG) This register: • Indicates when a channel trigger was generated • Enables the generation of a trigger when the FTM counter is equal to its initial • Selects which channels are used in the generation of the channel triggers Several channels can be selected to generate multiple triggers in one PWM period. Channels 6 and 7 are not used to generate channel triggers.
PAGE 867
Chapter 37 FlexTimer Module (FTM) FTMx_EXTTRIG field descriptions (continued) Field 5 CH1TRIG Description Channel 1 Trigger Enable Enable the generation of the channel trigger when the FTM counter is equal to the CnV register. 0 1 4 CH0TRIG Channel 0 Trigger Enable Enable the generation of the channel trigger when the FTM counter is equal to the CnV register. 0 1 3 CH5TRIG Enable the generation of the channel trigger when the FTM counter is equal to the CnV register.
PAGE 868
Memory map and register definition Address: Base address + 70h offset Bit R W 31 30 29 Reset 0 0 0 Bit R W 15 14 13 Reset 0 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 0 12 11 10 9 8 Reserved 0 0 0 0 POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 0 0 0 0 0 0 0 0 0 0 0 FTMx_POL field descriptions Field 31–8 Reserved 7 POL7 Description This field is reserved.
PAGE 869
Chapter 37 FlexTimer Module (FTM) FTMx_POL field descriptions (continued) Field Description This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 1 POL1 The channel polarity is active high. The channel polarity is active low. Channel 1 Polarity Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 0 POL0 The channel polarity is active high. The channel polarity is active low.
PAGE 870
Memory map and register definition 37.3.18 Fault Mode Status (FTMx_FMS) This register contains the fault detection flags, write protection enable bit, and the logic OR of the enabled fault inputs.
PAGE 871
Chapter 37 FlexTimer Module (FTM) FTMx_FMS field descriptions (continued) Field 6 WPEN Description Write Protection Enable The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPEN has no effect. 0 1 5 FAULTIN Write protection is disabled. Write protected bits can be written. Write protection is enabled. Write protected bits cannot be written.
PAGE 872
Memory map and register definition FTMx_FMS field descriptions (continued) Field Description If another fault condition is detected at the corresponding fault input before the clearing sequence is completed, the sequence is reset so FAULTF1 remains set after the clearing sequence is completed for the earlier fault condition. 0 1 0 FAULTF0 No fault condition was detected at the fault input. A fault condition was detected at the fault input.
PAGE 873
Chapter 37 FlexTimer Module (FTM) FTMx_FILTER field descriptions (continued) Field Description 11–8 CH2FVAL Channel 2 Input Filter Selects the filter value for the channel input. The filter is disabled when the value is zero. 7–4 CH1FVAL Channel 1 Input Filter Selects the filter value for the channel input. The filter is disabled when the value is zero. 3–0 CH0FVAL Channel 0 Input Filter Selects the filter value for the channel input. The filter is disabled when the value is zero. 37.3.
PAGE 874
Memory map and register definition FTMx_FLTCTRL field descriptions (continued) Field Description NOTE: Writing to this field has immediate effect and must be done only when the fault control or all fault inputs are disabled. Failure to do this could result in a missing fault detection. 7 FFLTR3EN Fault Input 3 Filter Enable Enables the filter for the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 6 FFLTR2EN Fault input filter is disabled.
PAGE 875
Chapter 37 FlexTimer Module (FTM) FTMx_FLTCTRL field descriptions (continued) Field Description 0 1 0 FAULT0EN Fault input is disabled. Fault input is enabled. Fault Input 0 Enable Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 Fault input is disabled. Fault input is enabled. 37.3.21 Quadrature Decoder Control And Status (FTMx_QDCTRL) This register has the control and status bits for the Quadrature Decoder mode.
PAGE 876
Memory map and register definition FTMx_QDCTRL field descriptions Field 31–8 Reserved 7 PHAFLTREN Description This field is reserved. This read-only field is reserved and always has the value 0. Phase A Input Filter Enable Enables the filter for the quadrature decoder phase A input. The filter value for the phase A input is defined by the CH0FVAL field of FILTER. The phase A filter is also disabled when CH0FVAL is zero.
PAGE 877
Chapter 37 FlexTimer Module (FTM) FTMx_QDCTRL field descriptions (continued) Field Description 0 QUADEN Quadrature Decoder Mode Enable Enables the Quadrature Decoder mode. In this mode, the phase A and B input signals control the FTM counter direction. The Quadrature Decoder mode has precedence over the other modes. See Table 37-7. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 Quadrature Decoder mode is disabled. Quadrature Decoder mode is enabled. 37.3.
PAGE 878
Memory map and register definition FTMx_CONF field descriptions (continued) Field Description 0 1 8 Reserved Use of an external global time base is disabled. Use of an external global time base is enabled. This field is reserved. This read-only field is reserved and always has the value 0. 7–6 BDMMODE BDM Mode Selects the FTM behavior in BDM mode. See BDM mode. 5 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
PAGE 879
Chapter 37 FlexTimer Module (FTM) FTMx_FLTPOL field descriptions (continued) Field 3 FLT3POL Description Fault Input 3 Polarity Defines the polarity of the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 2 FLT2POL The fault input polarity is active high. A one at the fault input indicates a fault. The fault input polarity is active low. A zero at the fault input indicates a fault. Fault Input 2 Polarity Defines the polarity of the fault input.
PAGE 880
Memory map and register definition 37.3.24 Synchronization Configuration (FTMx_SYNCONF) This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j = 0, 1, 2, when the hardware trigger j is detected.
PAGE 881
Chapter 37 FlexTimer Module (FTM) FTMx_SYNCONF field descriptions (continued) Field Description 15–13 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12 SWSOC Software output control synchronization is activated by the software trigger. 11 SWINVC Inverting control synchronization is activated by the software trigger. 10 SWOM 0 1 0 1 The software trigger does not activate the SWOCTRL register synchronization.
PAGE 882
Memory map and register definition FTMx_SYNCONF field descriptions (continued) Field Description 0 1 FTM clears the TRIGj bit when the hardware trigger j is detected. FTM does not clear the TRIGj bit when the hardware trigger j is detected. 37.3.25 FTM Inverting Control (FTMx_INVCTRL) This register controls when the channel (n) output becomes the channel (n+1) output, and channel (n+1) output becomes the channel (n) output.
PAGE 883
Chapter 37 FlexTimer Module (FTM) FTMx_INVCTRL field descriptions (continued) Field Description 0 INV0EN Pair Channels 0 Inverting Enable 0 1 Inverting is disabled. Inverting is enabled. 37.3.26 FTM Software Output Control (FTMx_SWOCTRL) This register enables software control of channel (n) output and defines the value forced to the channel (n) output: • The CHnOC bits enable the control of the corresponding channel (n) output by software.
PAGE 884
Memory map and register definition FTMx_SWOCTRL field descriptions (continued) Field Description 0 1 The software output control forces 0 to the channel output. The software output control forces 1 to the channel output.
PAGE 885
Chapter 37 FlexTimer Module (FTM) FTMx_SWOCTRL field descriptions (continued) Field Description 0 1 The channel output is not affected by software output control. The channel output is affected by software output control. 1 CH1OC Channel 1 Software Output Control Enable 0 CH0OC Channel 0 Software Output Control Enable 0 1 0 1 The channel output is not affected by software output control. The channel output is affected by software output control.
PAGE 886
Functional description FTMx_PWMLOAD field descriptions (continued) Field Description 8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7 CH7SEL Channel 7 Select 6 CH6SEL Channel 6 Select 5 CH5SEL Channel 5 Select 4 CH4SEL Channel 4 Select 3 CH3SEL Channel 3 Select 2 CH2SEL Channel 2 Select 1 CH1SEL Channel 1 Select 0 CH0SEL Channel 0 Select 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Do not include the channel in the matching process.
PAGE 887
Chapter 37 FlexTimer Module (FTM) FTM counting is up. Channel (n) is in high-true EPWM mode. PS[2:0] = 001 CNTIN = 0x0000 MOD = 0x0004 CnV = 0x0002 prescaler counter FTM counter 1 0 3 1 0 4 1 0 1 0 0 1 1 0 1 0 2 3 1 0 4 1 0 0 1 0 1 0 0 1 2 1 3 1 0 0 4 1 0 1 0 1 1 0 2 channel (n) output counter overflow channel (n) match counter overflow channel (n) match counter overflow channel (n) match Figure 37-166. Notation used 37.4.
PAGE 888
Functional description The external clock passes through a synchronizer clocked by the system clock to assure that counter transitions are properly aligned to system clock transitions.Therefore, to meet Nyquist criteria considering also jitter, the frequency of the external clock source must not exceed 1/4 of the system clock frequency. 37.4.2 Prescaler The selected counter clock source passes through a prescaler that is a 7-bit counter. The value of the prescaler is selected by the PS[2:0] bits.
PAGE 889
Chapter 37 FlexTimer Module (FTM) The FTM period when using up counting is (MOD – CNTIN + 0x0001) × period of the FTM counter clock. The TOF bit is set when the FTM counter changes from MOD to CNTIN. FTM counting is up.
PAGE 890
Functional description FTM counting is up CNTIN = 0x0000 MOD = 0x0004 FTM counter 3 4 0 1 2 3 4 0 1 2 3 0 4 1 2 TOF bit set TOF bit set TOF bit set TOF bit period of FTM counter clock period of counting = (MOD - CNTIN + 0x0001) x period of FTM counter clock = (MOD + 0x0001) x period of FTM counter clock Figure 37-169.
PAGE 891
Chapter 37 FlexTimer Module (FTM) FTM counting is up MOD = 0x0005 CNTIN = 0x0015 load of CNTIN FTM counter load of CNTIN 0x0005 0x0015 0x0016 ... 0xFFFE 0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0015 0x0016 ... TOF bit set TOF bit set TOF bit Figure 37-170. Example of up counting when the value of CNTIN is greater than the value of MOD 37.4.3.2 Up-down counting Up-down counting is selected when (QUADEN= 0) and (CPWMS = 1).
PAGE 892
Functional description FTM counting is up-down CNTIN = 0x0000 MOD = 0x0004 FTM counter 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 1 2 3 4 TOF bit set TOF bit period of FTM counter clock set TOF bit period of counting = 2 x (MOD - CNTIN) x period of FTM counter clock = 2 x MOD x period of FTM counter clock Figure 37-171. Example of up-down counting when CNTIN = 0x0000 Note It is expected that the up-down counting be used only with CNTIN = 0x0000. 37.4.3.
PAGE 893
Chapter 37 FlexTimer Module (FTM) 37.4.3.4 Counter reset Any write to CNT resets the FTM counter to the value in the CNTIN register and the channels output to its initial value, except for channels in Output Compare mode. The FTM counter synchronization can also be used to force the value of CNTIN into the FTM counter and the channels output to its initial value, except for channels in Output Compare mode. 37.4.3.
PAGE 894
Functional description • • • • • DECAPEN = 0 COMBINE = 0 CPWMS = 0 MSnB:MSnA = 0:0 ELSnB:ELSnA ≠ 0:0 When a selected edge occurs on the channel input, the current value of the FTM counter is captured into the CnV register, at the same time the CHnF bit is set and the channel interrupt is generated if enabled by CHnIE = 1. See the following figure. When a channel is configured for input capture, the FTMxCHn pin is an edge-sensitive input.
PAGE 895
Chapter 37 FlexTimer Module (FTM) Note The Input Capture mode must be used only with CNTIN = 0x0000. 37.4.4.1 Filter for Input Capture mode The filter function is only available on channels 0, 1, 2, and 3. First, the input signal is synchronized by the system clock. Following synchronization, the input signal enters the filter block. See the following figure.
PAGE 896
Functional description system clock divided by 4 channel (n) input after the synchronizer 5-bit counter CHnFVAL[3:0] = 0010 (binary value) Time filter output Figure 37-177. Channel input filter example 37.4.5 Output Compare mode The Output Compare mode is selected when: • • • • DECAPEN = 0 COMBINE = 0 CPWMS = 0, and MSnB:MSnA = 0:1 In Output Compare mode, the FTM can generate timed pulses with programmable position, polarity, duration, and frequency.
PAGE 897
Chapter 37 FlexTimer Module (FTM) MOD = 0x0005 CnV = 0x0003 CNT channel (n) output CHnF bit ... 2 1 0 counter overflow channel (n) match counter overflow 4 3 5 0 counter overflow channel (n) match 1 2 3 4 5 0 1 ... previous value previous value TOF bit Figure 37-179. Example of the Output Compare mode when the match clears the channel output MOD = 0x0005 CnV = 0x0003 channel (n) match counter overflow CNT channel (n) output CHnF bit ...
PAGE 898
Functional description The EPWM period is determined by (MOD − CNTIN + 0x0001) and the pulse width (duty cycle) is determined by (CnV − CNTIN). The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel (n) match (FTM counter = CnV), that is, at the end of the pulse width. This type of PWM signal is called edge-aligned because the leading edges of all PWM signals are aligned with the beginning of the period, which is the same for all channels within an FTM.
PAGE 899
Chapter 37 FlexTimer Module (FTM) MOD = 0x0008 CnV = 0x0005 counter overflow CNT ... 0 channel (n) match 1 2 3 4 5 counter overflow 6 7 8 0 1 2 ... channel (n) output CHnF bit previous value TOF bit Figure 37-183. EPWM signal with ELSnB:ELSnA = X:1 If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal and CHnF bit is not set even when there is the channel (n) match.
PAGE 900
Functional description The other channel modes are not compatible with the up-down counter (CPWMS = 1). Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1). FTM counter = CNTIN counter overflow FTM counter = MOD counter overflow FTM counter = MOD channel (n) match (FTM counting is up) channel (n) match (FTM counting is down) channel (n) output pulse width 2 x (CnV - CNTIN) period 2 x (MOD - CNTINCNTIN) Figure 37-184.
PAGE 901
Chapter 37 FlexTimer Module (FTM) counter overflow counter overflow MOD = 0x0008 CnV = 0x0005 channel (n) match in down counting CNT ... 7 8 7 6 5 4 3 channel (n) match in up counting 2 1 0 1 2 3 4 5 6 channel (n) match in down counting 7 8 7 6 5 ... channel (n) output CHnF bit previous value TOF bit Figure 37-186.
PAGE 902
Functional description The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (FTM counter = C(n)V). The CH(n+1)F bit is set and the channel (n +1) interrupt is generated, if CH(n+1)IE = 1, at the channel (n+1) match (FTM counter = C(n+1)V). If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced low at the beginning of the period (FTM counter = CNTIN) and at the channel (n+1) match (FTM counter = C(n +1)V).
PAGE 903
Chapter 37 FlexTimer Module (FTM) FTM counter MOD C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 37-188. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V < C(n+1)V) FTM counter MOD = C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 37-189.
PAGE 904
Functional description FTM counter MOD = C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 not fully 100% duty cycle not fully 0% duty cycle Figure 37-191. Channel (n) output if (CNTIN < C(n)V < MOD) and (C(n)V is Almost Equal to CNTIN) and (C(n+1)V = MOD) FTM counter MOD C(n+1)V C(n)V = CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 not fully 100% duty cycle not fully 0% duty cycle Figure 37-192.
PAGE 905
Chapter 37 FlexTimer Module (FTM) FTM counter C(n+1)V MOD CNTIN C(n)V channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 37-193. Channel (n) output if C(n)V and C(n+1)V are not between CNTIN and MOD FTM counter MOD C(n+1)V = C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 37-194.
PAGE 906
Functional description FTM counter MOD C(n)V = C(n+1)V = CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 0% duty cycle 100% duty cycle Figure 37-195. Channel (n) output if (C(n)V = C(n+1)V = CNTIN) FTM counter MOD = C(n+1)V = C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 0% duty cycle 100% duty cycle Figure 37-196.
PAGE 907
Chapter 37 FlexTimer Module (FTM) FTM counter MOD C(n+1)V CNTIN C(n)V channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 37-198. Channel (n) output if (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD) FTM counter MOD C(n)V CNTIN C(n+1)V channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 37-199.
PAGE 908
Functional description FTM counter C(n)V MOD C(n+1)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 37-200. Channel (n) output if (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD) FTM counter C(n+1)V MOD C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 37-201. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V < MOD) K20 Sub-Family Reference Manual, Rev. 1.
PAGE 909
Chapter 37 FlexTimer Module (FTM) FTM counter C(n+1)V MOD = C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 not fully 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 not fully 100% duty cycle Figure 37-202. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V = MOD) 37.4.8.
PAGE 910
Functional description channel (n+1) match FTM counter channel (n) match channel (n) output with ELSnB:ELSnA = 1:0 channel (n+1) output with COMP = 0 channel (n+1) output with COMP = 1 Figure 37-203. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = 1:0) channel (n+1) match FTM counter channel (n) match channel (n) output with ELSnB:ELSnA = X:1 channel (n+1) output with COMP = 0 channel (n+1) output with COMP = 1 Figure 37-204.
PAGE 911
Chapter 37 FlexTimer Module (FTM) 37.4.10.2 MOD register update The following table describes when MOD register is updated: Table 37-244. MOD register update When CLKS[1:0] = 0:0 Then MOD register is updated When MOD register is written, independent of FTMEN bit. • CLKS[1:0] ≠ 0:0, and • FTMEN = 0 According to the CPWMS bit, that is: • If the selected mode is not CPWM then MOD register is updated after MOD register was written and the FTM counter changes from MOD to CNTIN.
PAGE 912
Functional description 37.4.11 PWM synchronization The PWM synchronization provides an opportunity to update the MOD, CNTIN, CnV, OUTMASK, INVCTRL and SWOCTRL registers with their buffered value and force the FTM counter to the CNTIN register value. Note • The PWM synchronization must be used only in Combine mode. • The legacy PWM synchronization (SYNCMODE = 0) is a subset of the enhanced PWM synchronization (SYNCMODE = 1). Thus, only the enhanced PWM synchronization must be used. 37.4.11.
PAGE 913
Chapter 37 FlexTimer Module (FTM) system clock write 1 to TRIG0 bit TRIG0 bit trigger_0 input synchronized trigger_0 by system clock trigger 0 event Note All hardware trigger inputs have the same behavior. Figure 37-205. Hardware trigger event with HWTRIGMODE = 0 If HWTRIGMODE = 1, then the TRIGn bit is only cleared when 0 is written to it. NOTE The HWTRIGMODE bit must be 1 only with enhanced PWM synchronization (SYNCMODE = 1). 37.4.11.
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Functional description system clock write 1 to SWSYNC bit SWSYNC bit software trigger event PWM synchronization selected loading point Figure 37-206. Software trigger event 37.4.11.3 Boundary cycle and loading points The boundary cycle definition is important for the loading points for the registers MOD, CNTIN, and C(n)V. In Up counting mode, the boundary cycle is defined as when the counter wraps to its initial value (CNTIN).
PAGE 915
Chapter 37 FlexTimer Module (FTM) loading points if CNTMAX = 1 or CNTMIN = 1 CNT = MOD -> CNTIN up counting mode loading points if CNTMAX = 1 CNT = (MOD - 0x0001) -> MOD up-down counting mode CNT = (CNTIN + 0x0001) -> CNTIN loading points if CNTMIN = 1 Figure 37-207. Boundary cycles and loading points 37.4.11.4 MOD register synchronization The MOD register synchronization updates the MOD register with its buffer value. This synchronization is enabled if (FTMEN = 1).
PAGE 916
Functional description begin legacy PWM synchronization SYNCMODE bit ? =0 =1 enhanced PWM synchronization MOD register is updated by hardware trigger MOD register is updated by software trigger HWWRBUF = 0 bit ? SWWRBUF = 0 bit ? =1 =1 end software trigger 0= SWSYNC bit ? end hardware trigger TRIGn bit ? =1 =0 =1 FTM counter is reset by software trigger SWRSTCNT bit ? wait hardware trigger n =1 =0 wait the next selected loading point HWTRIGMODE bit ? =1 =0 update MOD with its buf
PAGE 917
Chapter 37 FlexTimer Module (FTM) loading point. If the trigger event was a hardware trigger, then the trigger enable bit (TRIGn) is cleared according to Hardware trigger. Examples with software and hardware triggers follow. system clock write 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point MOD register is updated Figure 37-209.
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Functional description system clock write 1 to SWSYNC bit SWSYNC bit software trigger event MOD register is updated Figure 37-211. MOD synchronization with (SYNCMODE = 0), (PWMSYNC = 0), (REINIT = 1), and software trigger was used system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event MOD register is updated Figure 37-212.
PAGE 919
Chapter 37 FlexTimer Module (FTM) 37.4.11.5 CNTIN register synchronization The CNTIN register synchronization updates the CNTIN register with its buffer value. This synchronization is enabled if (FTMEN = 1), (SYNCMODE = 1), and (CNTINC = 1). The CNTIN register synchronization can be done only by the enhanced PWM synchronization (SYNCMODE = 1). The synchronization mechanism is the same as the MOD register synchronization done by the enhanced PWM synchronization; see MOD register synchronization. 37.4.11.
PAGE 920
Functional description begin update OUTMASK register at each rising edge of system clock no = 0= SYNCHOM bit ? update OUTMASK register by PWM synchronization =1 1= rising edge of system clock ? SYNCMODE bit ? =0 legacy PWM synchronization = yes update OUTMASK with its buffer value end enhanced PWM synchronization OUTMASK is updated by hardware trigger OUTMASK is updated by software trigger 1= 0= SWSYNC bit ? SWOM bit ? software trigger =0 end 0= end HWOM bit ? =1 hardware trigger TRI
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Chapter 37 FlexTimer Module (FTM) If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 0), then this synchronization is done on the next enabled trigger event. If the trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected loading point. If the trigger event was a hardware trigger, then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow.
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Functional description system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event OUTMASK register is updated and TRIG0 bit is cleared Figure 37-217. OUTMASK synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (SYNCHOM = 1), (PWMSYNC = 1), and a hardware trigger was used 37.4.11.8 INVCTRL register synchronization The INVCTRL register synchronization updates the INVCTRL register with its buffer value.
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Chapter 37 FlexTimer Module (FTM) begin update INVCTRL register at each rising edge of system clock 0= INVC bit ? =1 update INVCTRL register by PWM synchronization 1= no = rising edge of system clock ? SYNCMODE bit ? =0 end = yes update INVCTRL with its buffer value end enhanced PWM synchronization INVCTRL is updated by hardware trigger INVCTRL is updated by software trigger 1= 0= SWSYNC bit ? SWINVC bit ? software trigger =0 end 0= end HWINVC bit ? hardware trigger TRIGn bit ? =0 =
PAGE 924
Functional description The SWOCTRL register can be updated at each rising edge of system clock (SWOC = 0) or by the enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the SWOCTRL register synchronization depends on SWSOC and HWSOC bits.
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Chapter 37 FlexTimer Module (FTM) 37.4.11.10 FTM counter synchronization The FTM counter synchronization is a mechanism that allows the FTM to restart the PWM generation at a certain point in the PWM period. The channels outputs are forced to their initial value, except for channels in Output Compare mode, and the FTM counter is forced to its initial counting value defined by CNTIN register. The following figure shows the FTM counter synchronization.
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Functional description begin legacy PWM synchronization SYNCMODE bit ? =0 =1 enhanced PWM synchronization FTM counter is reset by software trigger SWSYNC bit ? SWRSTCNT bit ? software trigger =0 end =0 1= FTM counter is reset by hardware trigger end HWRSTCNT bit ? =1 hardware trigger TRIGn bit ? =0 =1 =0 =1 update FTM counter with CNTIN register value update the channels outputs with their initial value clear SWSYNC bit wait hardware trigger n update FTM counter with CNTIN registe
PAGE 927
Chapter 37 FlexTimer Module (FTM) system clock write 1 to SWSYNC bit SWSYNC bit software trigger event FTM counter is updated with the CNTIN register value and channel outputs are forced to their initial value Figure 37-222.
PAGE 928
Functional description 37.4.12 Inverting The invert functionality swaps the signals between channel (n) and channel (n+1) outputs. The inverting operation is selected when (FTMEN = 1), (QUADEN = 0), (DECAPEN = 0), (COMBINE = 1), (COMP = 1), (CPWMS = 0), and (INVm = 1), where m represents a channel pair.
PAGE 929
Chapter 37 FlexTimer Module (FTM) channel (n+1) match FTM counter channel (n) match channel (n) output before the inverting channel (n+1) output before the inverting write 1 to INV(m) bit INV(m) bit buffer INVCTRL register synchronization INV(m) bit channel (n) output after the inverting channel (n+1) output after the inverting NOTE INV(m) bit selects the inverting to the pair channels (n) and (n+1). Figure 37-226.
PAGE 930
Functional description channel (n+1) match FTM counter channel (n) match channel (n) output after the software output control channel (n+1) output after the software output control CH(n)OC buffer CH(n+1)OC buffer write to SWOCTRL register write to SWOCTRL register CH(n)OC bit CH(n+1)OC bit SWOCTRL register synchronization SWOCTRL register synchronization NOTE CH(n)OCV = 1 and CH(n+1)OCV = 0. Figure 37-227.
PAGE 931
Chapter 37 FlexTimer Module (FTM) Note • The software output control feature must be used only in Combine mode. • The CH(n)OC and CH(n+1)OC bits should be equal. • The COMP bit must not be modified when software output control is enabled, that is, CH(n)OC = 1 and/or CH(n +1)OC = 1. • Software output control has the same behavior with disabled or enabled FTM counter (see the CLKS bitfield description in the Status and Control register). 37.4.
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Functional description channel (n+1) match FTM counter channel (n) match channel (n) output (before deadtime insertion) channel (n+1) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (after deadtime insertion) Figure 37-228.
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Chapter 37 FlexTimer Module (FTM) • and the deadtime delay is greater than or equal to the channel (n) duty cycle ((C(n +1)V – C(n)V) × system clock), then the channel (n) output is always the inactive value (POL(n) bit value). • and the deadtime delay is greater than or equal to the channel (n+1) duty cycle ((MOD – CNTIN + 1 – (C(n+1)V – C(n)V) ) × system clock), then the channel (n+1) output is always the inactive value (POL(n+1) bit value).
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Functional description 37.4.15 Output mask The output mask can be used to force channels output to their inactive state through software. For example: to control a BLDC motor. Any write to the OUTMASK register updates its write buffer. The OUTMASK register is updated with its buffer value by PWM synchronization; see OUTMASK register synchronization. If CHnOM = 1, then the channel (n) output is forced to its inactive state (POLn bit value).
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Chapter 37 FlexTimer Module (FTM) Note The output mask feature must be used only in Combine mode. 37.4.16 Fault control The fault control is enabled if (FTMEN = 1) and (FAULTM[1:0] ≠ 0:0). FTM can have up to four fault inputs. FAULTnEN bit (where n = 0, 1, 2, 3) enables the fault input n and FFLTRnEN bit enables the fault input n filter. FFVAL[3:0] bits select the value of the enabled filter in each enabled fault input.
PAGE 936
Functional description (FFVAL[3:0] 0000) and (FFLTRnEN*) FLTnPOL synchronizer fault input n* value 0 fault input n* system clock D Q CLK D Q CLK Fault filter (5-bit counter) 1 fault input polarity control rising edge detector FAULTFn* * where n = 3, 2, 1, 0 Figure 37-233. Fault input n control block diagram If the fault control and fault input n are enabled and a rising edge at the fault input n signal is detected, a fault condition has occurred and the FAULTFn bit is set.
PAGE 937
Chapter 37 FlexTimer Module (FTM) 37.4.16.1 Automatic fault clearing If the automatic fault clearing is selected (FAULTM[1:0] = 1:1), then the channels output disabled by fault control is again enabled when the fault input signal (FAULTIN) returns to zero and a new PWM cycle begins. See the following figure.
PAGE 938
Functional description the beginning of new PWM cycles FTM counter channel (n) output (before fault control) FAULTIN bit channel (n) output (after fault control with manual fault clearing and POLn=0) FAULTF bit FAULTF bit is cleared NOTE The channel (n) output is after the fault control with manual fault clearing and POLn = 0. Figure 37-236. Fault control with manual fault clearing 37.4.16.
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Chapter 37 FlexTimer Module (FTM) Note The polarity control must be used only in Combine mode. 37.4.18 Initialization The initialization forces the CHnOI bit value to the channel (n) output when a one is written to the INIT bit. The initialization depends on COMP and DTEN bits. The following table shows the values that channels (n) and (n+1) are forced by initialization when the COMP and DTEN bits are zero. Table 37-249.
PAGE 940
Functional description pair channels (m) - channels (n) and (n+1) FTM counter QUADEN DECAPEN COMBINE(m) CPWMS C(n)V MS(n)B CH(n)OC MS(n)A CH(n)OCV POL(n) ELS(n)B CH(n+1)OC POL(n+1) ELS(n)A CH(n)OI CH(n+1)OI COMP(m) INV(m)EN CH(n+1)OCV CH(n)OM DTEN(m) CH(n+1)OM FAULTEN(m) channel (n) output signal generation of channel (n) output signal initialization complementary mode inverting software output control deadtime insertion output mask fault control polarity control channel (n+1) outpu
PAGE 941
Chapter 37 FlexTimer Module (FTM) The FTM is able to generate multiple triggers in one PWM period. Because each trigger is generated for a specific channel, several channels are required to implement this functionality. This behavior is described in the following figure.
PAGE 942
Functional description • When there is the FTM counter synchronization • If (CNT = CNTIN), (CLKS[1:0] = 0:0), and a value different from zero is written to CLKS[1:0] bits The following figures show these cases. CNTIN = 0x0000 MOD = 0x000F CPWMS = 0 system clock FTM counter 0x0C 0x0D 0x0E 0x0F 0x00 0x01 0x02 0x03 0x04 0x05 initialization trigger Figure 37-239.
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Chapter 37 FlexTimer Module (FTM) CNTIN = 0x0000 MOD = 0x000F CPWMS = 0 system clock 0x00 FTM counter 0x01 0x02 0x03 0x04 0x05 00 CLKS[1:0] bits 01 initialization trigger Figure 37-242. Initialization trigger is generated if (CNT = CNTIN), (CLKS[1:0] = 0:0), and a value different from zero is written to CLKS[1:0] bits The initialization trigger output provides a trigger signal that is used for on-chip modules. Note The initialization trigger must be used only in Combine mode. 37.4.
PAGE 944
Functional description FTM counter clock set CAPTEST clear CAPTEST write to MODE CAPTEST bit FTM counter 0x1053 0x1054 0x1055 0x1056 0x78AC 0x78AD 0x78AE0x78AF 0x78B0 write 0x78AC write to CNT CHnF bit 0x78AC 0x0300 CnV NOTE - FTM counter configuration: (FTMEN = 1), (QUADEN = 0), (CAPTEST = 1), (CPWMS = 0), (CNTIN = 0x0000), and (MOD = 0xFFFF) - FTM channel n configuration: input capture mode - (DECAPEN = 0), (COMBINE = 0), and (MSnB:MSnA = 0:0) Figure 37-243. Capture Test mode 37.4.
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Chapter 37 FlexTimer Module (FTM) Table 37-252. Clear CHnF bit when DMA = 1 CHnIE How CHnF Bit Can Be Cleared 0 CHnF bit is cleared either when the channel DMA transfer is done or by reading CnSC while CHnF is set and then writing a 0 to CHnF bit. 1 CHnF bit is cleared when the channel DMA transfer is done. 37.4.24 Dual Edge Capture mode The Dual Edge Capture mode is selected if FTMEN = 1 and DECAPEN = 1.
PAGE 946
Functional description The C(n)V register stores the value of FTM counter when the selected edge by channel (n) is detected at channel (n) input. The C(n+1)V register stores the value of FTM counter when the selected edge by channel (n+1) is detected at channel (n) input. In this mode, a coherency mechanism ensures coherent data when the C(n)V and C(n +1)V registers are read. The only requirement is that C(n)V must be read before C(n +1)V.
PAGE 947
Chapter 37 FlexTimer Module (FTM) 37.4.24.2 Continuous Capture mode The Continuous Capture mode is selected when (FTMEN = 1), (DECAPEN = 1), and (MS(n)A = 1). In this capture mode, the edges at the channel (n) input are captured continuously. The ELS(n)B:ELS(n)A bits select the initial edge to be captured, and ELS(n+1)B:ELS(n+1)A bits select the final edge to be captured. The edge captures are enabled while DECAP bit is set.
PAGE 948
Functional description 4 FTM counter 12 8 3 7 2 6 1 16 11 10 5 20 15 14 9 13 24 19 18 17 28 23 27 22 26 21 25 channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)V 1 3 5 7 9 15 2 4 6 8 10 16 19 CH(n)F bit clear CH(n)F C(n+1)V 20 22 24 CH(n+1)F bit clear CH(n+1)F problem 1 problem 2 Note - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
PAGE 949
Chapter 37 FlexTimer Module (FTM) 4 FTM counter 12 8 3 7 2 6 1 16 11 10 5 20 15 14 9 13 24 19 18 17 28 23 27 22 26 21 25 channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)V 1 3 5 7 9 11 15 19 21 23 2 4 6 8 10 12 16 20 22 24 CH(n)F bit clear CH(n)F C(n+1)V CH(n+1)F bit clear CH(n+1)F Note - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user. Figure 37-246.
PAGE 950
Functional description The following figure shows an example of the Dual Edge Capture – One-Shot mode used to measure the period between two consecutive rising edges. The DECAPEN bit selects the Dual Edge Capture mode, so it remains set. The DECAP bit is set to enable the measurement of next period. The CH(n)F bit is set when the first rising edge is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits.
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Chapter 37 FlexTimer Module (FTM) when the second rising edge is detected, that is, the edge selected by ELS(n+1)B:ELS(n +1)A bits. The CH(n+1)F bit indicates when two edges of the period were captured and the C(n)V and C(n+1)V registers are ready for reading.
PAGE 952
Functional description When a rising edge occurs in the channel (n) input signal, the FTM counter value is captured into channel (n) capture buffer. The channel (n) capture buffer value is transferred to C(n)V register when a falling edge occurs in the channel (n) input signal. C(n)V register has the FTM counter value when the previous rising edge occurred, and the channel (n) capture buffer has the FTM counter value when the last rising edge occurred.
PAGE 953
Chapter 37 FlexTimer Module (FTM) PHAFLTREN CH0FVAL[3:0] synchronizer CNTIN 0 phase A input system clock Q D CLK D PHAPOL 1 Filter CLK MOD filtered phase A signal Q PHBPOL FTM counter PHBFLTREN FTM counter enable up/down direction CH1FVAL[3:0] TOFDIR synchronizer QUADIR 0 phase B input Q D D Q filtered phase B signal CLK CLK Filter 1 Figure 37-250.
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Functional description phase B (counting direction) phase A (counting rate) FTM counter increment/decrement +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 FTM counter MOD CNTIN 0x0000 Time Figure 37-251. Quadrature Decoder – Count and Direction Encoding mode If QUADMODE = 0, then the Phase A and Phase B Encoding mode is enabled; see the following figure. In this mode, the relationship between phase A and B signals indicates the counting direction, and phase A and B signals define the counting rate.
PAGE 955
Chapter 37 FlexTimer Module (FTM) phase A phase B FTM counter increment/decrement +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 FTM counter MOD CNTIN 0x0000 Time Figure 37-252. Quadrature Decoder – Phase A and Phase B Encoding mode The following figure shows the FTM counter overflow in up counting. In this case, when the FTM counter changes from MOD to CNTIN, TOF and TOFDIR bits are set.
PAGE 956
Functional description phase A phase B FTM counter increment/decrement -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 FTM counter MOD CNTIN 0x0000 Time set TOF clear TOFDIR set TOF clear TOFDIR Figure 37-254. FTM counter overflow in down counting for Quadrature Decoder mode 37.4.25.1 Quadrature Decoder boundary conditions The following figures show the FTM counter responding to motor jittering typical in motor position control applications.
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Chapter 37 FlexTimer Module (FTM) phase A phase B FTM counter MOD CNTIN 0x0000 Time Figure 37-256. Motor position jittering near maximum and minimum count value The first highlighted transition causes a jitter on the FTM counter value near the maximum count value (MOD). The second indicated transition occurs on phase A and causes the FTM counter transition between the maximum and minimum count values which are defined by MOD and CNTIN registers.
PAGE 958
Functional description Table 37-253. FTM behavior when the chip Is in BDM mode (continued) BDMMODE 11 FTM Counter Functional mode CH(n)F Bit FTM Channels Output Writes to MOD, CNTIN, and C(n)V Registers can be set Functional mode Functional mode Note that if BDMMODE[1:0] = 2’b00 then the channels outputs remain at the value when the chip enters in BDM mode, because the FTM counter is stopped. However, the following situations modify the channels outputs in this BDM mode.
PAGE 959
Chapter 37 FlexTimer Module (FTM) The following figure shows some examples of enabled loading points.
PAGE 960
Functional description • • • • NOTE If ELSjB and ELSjA bits are different from zero, then the channel (j) output signal is generated according to the configured output mode. If ELSjB and ELSjA bits are zero, then the generated signal is not available on channel (j) output. If CHjIE = 1, then the channel (j) interrupt is generated when the channel (j) match occurs. At the intermediate load neither the channels outputs nor the FTM counter are changed.
PAGE 961
Chapter 37 FlexTimer Module (FTM) In the configuration described in the preceding figure, FTM modules A and B have their FTM counters enabled if at least one of the gtb_out signals from one of the FTM modules is 1. There are several possible configurations for the interconnection of the gtb_in and gtb_out signals, represented by the example glue logic shown in the figure. Note that these configurations are chip-dependent and implemented outside of the FTM modules.
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Reset overview When the FTM exits from reset: • the FTM counter and the prescaler counter are zero and are stopped (CLKS[1:0] = 00b); • the timer overflow interrupt is zero, see Timer Overflow Interrupt; • the channels interrupts are zero, see Channel (n) Interrupt; • the fault interrupt is zero, see Fault Interrupt; • the channels are in input capture mode, see Input Capture mode; • the channels outputs are zero; • the channels pins are not controlled by FTM (ELS(n)B:ELS(n)A = 0:0) (../dil/ FTM.
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Chapter 37 FlexTimer Module (FTM) The following figure shows an example when the channel (n) is in Output Compare mode and the channel (n) output is toggled when there is a match. In the Output Compare mode, the channel output is not updated to its initial value when there is a write to CNT register (item 3). In this case, use the software output control (Software output control) or the initialization (Initialization) to update the channel output to the selected value (item 4).
PAGE 964
FTM Interrupts K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 964 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 965
Chapter 38 Periodic Interrupt Timer (PIT) 38.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels. 38.1.1 Block diagram The following figure shows the block diagram of the PIT module. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
PAGE 966
Signal description PIT Peripheral bus PIT registers load_value Timer 1 Iinterrupts Triggers Timer n Peripheral bus clock Figure 38-1. Block diagram of the PIT NOTE See the chip configuration details for the number of PIT channels used in this MCU. 38.1.2 Features The main features of this block are: • Ability of timers to generate DMA trigger pulses • Ability of timers to generate interrupts • Maskable interrupts • Independent timeout periods for each timer 38.
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Chapter 38 Periodic Interrupt Timer (PIT) 38.3 Memory map/register description This section provides a detailed description of all registers accessible in the PIT module. NOTE • Reserved registers will read as 0, writes will have no effect. • See the chip configuration details for the number of PIT channels used in this MCU. PIT memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4003_7000 PIT Module Control Register (PIT_MCR) 32 R/W 0000_0002h 38.3.
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Memory map/register description 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 MDIS FRZ 1 0 0 PIT_MCR field descriptions Field Description 31–2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 MDIS Module Disable Disables the module clock. This field must be enabled before any other setup is done. 0 1 0 FRZ Clock for PIT timers is enabled. Clock for PIT timers is disabled.
PAGE 969
Chapter 38 Periodic Interrupt Timer (PIT) 38.3.3 Current Timer Value Register (PIT_CVALn) These registers indicate the current timer position.
PAGE 970
Memory map/register description PIT_TCTRLn field descriptions (continued) Field Description 0 1 1 TIE Timer is not chained. Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. Timer Interrupt Enable When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt will immediately cause an interrupt event. To avoid this, the associated TFLGn[TIF] must be cleared first. 0 1 0 TEN Interrupt requests from Timer n are disabled.
PAGE 971
Chapter 38 Periodic Interrupt Timer (PIT) 38.4 Functional description This section provides the functional description of the module. 38.4.1 General operation This section gives detailed information on the internal operation of the module. Each timer can be used to generate trigger pulses and interrupts. Each interrupt is available on a separate interrupt line. 38.4.1.1 Timers The timers generate triggers at periodic intervals, when enabled.
PAGE 972
Functional description Timer enabled Start value = p1 Re-enable Disable timer, Set new load value timer Trigger event p2 p1 p2 p2 p1 Figure 38-24. Modifying running timer period It is also possible to change the counter period without restarting the timer by writing LDVAL with the new load value. This value will then be loaded after the next trigger event. See the following figure. Timer enabled Start value = p1 New start Value p2 set Trigger event p1 p1 p1 p2 p2 Figure 38-25.
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Chapter 38 Periodic Interrupt Timer (PIT) 38.4.3 Chained timers When a timer has chain mode enabled, it will only count after the previous timer has expired. So if timer n-1 has counted down to 0, counter n will decrement the value by one. This allows to chain some of the timers together to form a longer timer. The first timer (timer 0) cannot be chained to any other timer. 38.5 Initialization and application information In the example configuration: • The PIT clock has a frequency of 50 MHz.
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Example configuration for chained timers 38.6 Example configuration for chained timers In the example configuration: • The PIT clock has a frequency of 100 MHz. • Timers 1 and 2 are available. • An interrupt shall be raised every 1 hour. The PIT module needs to be activated by writing a 0 to MCR[MDIS]. The 100 MHz clock frequency equates to a clock period of 10 ns, so the PIT needs to count for 6000 million cycles, which is more than a single timer can do.
PAGE 975
Chapter 39 Low-Power Timer (LPTMR) 39.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. 39.1.
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LPTMR signal descriptions Table 39-1. Modes of operation Modes Description Run The LPTMR operates normally. Wait The LPTMR continues to operate normally and may be configured to exit the low-power mode by generating an interrupt request. Stop The LPTMR continues to operate normally and may be configured to exit the low-power mode by generating an interrupt request.
PAGE 977
Chapter 39 Low-Power Timer (LPTMR) 39.3 Memory map and register definition NOTE The LPTMR registers are reset only on a POR or LVD event. See LPTMR power and reset for more details. LPTMR memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4004_0000 Low Power Timer Control Status Register (LPTMR0_CSR) 32 R/W 0000_0000h 39.3.1/977 4004_0004 Low Power Timer Prescale Register (LPTMR0_PSR) 32 R/W 0000_0000h 39.3.
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Memory map and register definition LPTMRx_CSR field descriptions (continued) Field Description 0 1 5–4 TPS Timer Pin Select Configures the input source to be used in Pulse Counter mode. TPS must be altered only when the LPTMR is disabled. The input connections vary by device. See the chip configuration details for information on the connections to these inputs. 00 01 10 11 3 TPP Configures the polarity of the input source in Pulse Counter mode. TPP must be changed only when the LPTMR is disabled.
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Chapter 39 Low-Power Timer (LPTMR) 39.3.
PAGE 980
Memory map and register definition LPTMRx_PSR field descriptions (continued) Field Description 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
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Chapter 39 Low-Power Timer (LPTMR) 39.3.4 Low Power Timer Counter Register (LPTMRx_CNR) Address: 4004_0000h base + Ch offset = 4004_000Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 COUNTER W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTMRx_CNR field descriptions Field 31–16 Reserved 15–0 COUNTER Description This field is reserved.
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Functional description In Pulse Counter mode with the prescaler/glitch filter bypassed, the selected input source directly clocks the CNR and no other clock source is required. To minimize power in this case, configure the prescaler clock source for a clock that is not toggling. NOTE The clock source or pulse input source selected for the LPTMR should not exceed the frequency fLPTMR defined in the device datasheet. 39.4.
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Chapter 39 Low-Power Timer (LPTMR) 39.4.3.3 Glitch filter In Pulse Counter mode, when the glitch filter is enabled, the output of the glitch filter directly clocks the CNR. When the LPTMR is first enabled, the output of the glitch filter is asserted, that is, logic 1 for active-high and logic 0 for active-low. The following table shows the change in glitch filter output with the selected input source.
PAGE 984
Functional description 39.4.5 LPTMR counter The CNR increments by one on every: • • • • Prescaler clock in Time Counter mode with prescaler bypassed Prescaler output in Time Counter mode with prescaler enabled Input source assertion in Pulse Counter mode with glitch filter bypassed Glitch filter output in Pulse Counter mode with glitch filter enabled The CNR is reset when the LPTMR is disabled or if the counter register overflows. If CSR[TFC] is set, then the CNR is also reset whenever CSR[TCF] is set.
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Chapter 40 Carrier Modulator Transmitter (CMT) 40.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The carrier modulator transmitter (CMT) module provides the means to generate the protocol timing and carrier signals for a wide variety of encoding schemes.
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Block diagram • Baseband • Frequency-shift key (FSK) • Direct software control of the IRO signal • Extended space operation in Time, Baseband, and FSK modes • Selectable input clock divider • Interrupt on end-of-cycle • Ability to disable the IRO signal and use as timer interrupt 40.3 Block diagram The following figure presents the block diagram of the CMT module. K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 986 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 40 Carrier Modulator Transmitter (CMT) CMT Carrier generator Modulator CMT_IRO CMT Interrupts CMT registers divider_enable Clock divider Peripheral bus clock Peripheral bus Figure 40-1. CMT module block diagram 40.4 Modes of operation The following table describes the operation of the CMT module operates in various modes. Table 40-1.
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Modes of operation Table 40-1. Modes of operation (continued) Modes Description Frequency-shift key This mode allows the carrier generator to alternate between two sets of high and low times. When operating in FSK mode, the generator will toggle between the two sets when instructed by the modulator, allowing the user to dynamically switch between two carrier frequencies without CPU intervention. The following table summarizes the modes of operation of the CMT module. Table 40-2.
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Chapter 40 Carrier Modulator Transmitter (CMT) 40.4.2 Stop mode operation This section describes the CMT Stop mode operations. 40.4.2.1 Normal Stop mode operation During Normal Stop mode, clocks to the CMT module are halted. No registers are affected. The CMT module will resume upon exit from Normal Stop mode because the clocks are halted.
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Memory map/register definition 40.5.1 CMT_IRO — Infrared Output This output signal is driven by the modulator output when MSC[MCGEN] and OC[IROPEN] are set. The IRO signal starts a valid transmission with a delay, after MSC[MCGEN] bit be asserted to high, that can be calculated based on two register bits. Table 40-5 shows how to calculate this delay. The following table describes conditions for the IRO signal to be active.
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Chapter 40 Carrier Modulator Transmitter (CMT) CMT memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_2007 CMT Modulator Data Register Mark Low (CMT_CMD2) 8 R/W Undefined 40.6.8/997 4006_2008 CMT Modulator Data Register Space High (CMT_CMD3) 8 R/W Undefined 40.6.9/997 4006_2009 CMT Modulator Data Register Space Low (CMT_CMD4) 8 R/W Undefined 40.6.
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Memory map/register definition 40.6.2 CMT Carrier Generator Low Data Register 1 (CMT_CGL1) This data register contains the primary low value for generating the carrier output. Address: 4006_2000h base + 1h offset = 4006_2001h Bit 7 Read Write Reset 6 5 4 3 2 1 0 x* x* x* x* PL x* x* x* x* * Notes: • x = Undefined at reset.
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Chapter 40 Carrier Modulator Transmitter (CMT) CMT_CGH2 field descriptions (continued) Field Description The secondary carrier high time value is undefined out of reset. This register must be written to nonzero values before the carrier generator is enabled when operating in FSK mode. 40.6.4 CMT Carrier Generator Low Data Register 2 (CMT_CGL2) This data register contains the secondary low value for generating the carrier output.
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Memory map/register definition CMT_OC field descriptions Field Description 7 IROL IRO Latch Control Reads the state of the IRO latch. Writing to IROL changes the state of the IRO signal when MSC[MCGEN] is cleared and IROPEN is set. 6 CMTPOL CMT Output Polarity Controls the polarity of the IRO signal. 0 The IRO signal is active-low. 1 The IRO signal is active-high. 5 IROPEN IRO Pin Enable Enables and disables the IRO signal.
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Chapter 40 Carrier Modulator Transmitter (CMT) CMT_MSC field descriptions (continued) Field Description • The modulator is not currently active and MCGEN is set to begin the initial CMT transmission. • At the end of each modulation cycle while MCGEN is set. This is recognized when a match occurs between the contents of the space period register and the down counter.
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Memory map/register definition CMT_MSC field descriptions (continued) Field Description 0 CPU interrupt is disabled. 1 CPU interrupt is enabled. 0 MCGEN Modulator and Carrier Generator Enable Setting MCGEN will initialize the carrier generator and modulator and will enable all clocks. When enabled, the carrier generator and modulator will function continuously.
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Chapter 40 Carrier Modulator Transmitter (CMT) 40.6.8 CMT Modulator Data Register Mark Low (CMT_CMD2) The contents of this register are transferred to the modulator down counter upon the completion of a modulation period. Address: 4006_2000h base + 7h offset = 4006_2007h Bit Read Write Reset 7 6 5 4 3 2 1 0 x* x* x* x* MB[7:0] x* x* x* x* * Notes: • x = Undefined at reset.
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Memory map/register definition 40.6.10 CMT Modulator Data Register Space Low (CMT_CMD4) The contents of this register are transferred to the space period register upon the completion of a modulation period. Address: 4006_2000h base + 9h offset = 4006_2009h Bit Read Write Reset 7 6 5 4 3 2 1 0 x* x* x* x* 1 0 0 0 SB[7:0] x* x* x* x* * Notes: • x = Undefined at reset.
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Chapter 40 Carrier Modulator Transmitter (CMT) CMT_PPS field descriptions (continued) Field Description 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bus clock ÷ 5 Bus clock ÷ 6 Bus clock ÷ 7 Bus clock ÷ 8 Bus clock ÷ 9 Bus clock ÷ 10 Bus clock ÷ 11 Bus clock ÷ 12 Bus clock ÷ 13 Bus clock ÷ 14 Bus clock ÷ 15 Bus clock ÷ 16 40.6.12 CMT Direct Memory Access Register (CMT_DMA) This register is used to enable/disable direct memory access (DMA).
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Functional description 40.7 Functional description The CMT module primarily consists of clock divider, carrier generator, and modulator. 40.7.1 Clock divider The CMT was originally designed to be based on an 8 MHz bus clock that could be divided by 1, 2, 4, or 8 according to the specification. To be compatible with higher bus frequency, the primary prescaler (PPS) was developed to receive a higher frequency and generate a clock enable signal called intermediate frequency (IF).
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Chapter 40 Carrier Modulator Transmitter (CMT) Table 40-19. Clock divider Bus clock (MHz) MSC[CMTDIV] Carrier generator resolution (μs) Min. Min. carrier generator period modulator period (μs) (μs) 8 00 0.125 0.25 1.0 8 01 0.25 0.5 2.0 8 10 0.5 1.0 4.0 8 11 1.0 2.0 8.0 The possible duty cycle options depend upon the number of counts required to complete the carrier period. For example, 1.
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Functional description Secondary High Count Register CMTCLK BASE FSK MCGEN CARRIER OUT (fcg) Clock and output control Primary High Count Register =? CLK CLR 8-bit up counter Primary/ Secondary Select =? Secondary Low Count Register Primary Low Count Register Figure 40-15. Carrier generator block diagram The high/low time counter is an 8-bit up counter. After each increment, the contents of the counter are compared with the appropriate high or low count value register.
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Chapter 40 Carrier Modulator Transmitter (CMT) The duty cycle of the carrier signal is controlled by varying the ratio of high time to low + high time. As the input clock period is fixed, the duty cycle resolution will be proportional to the number of counts required to generate the desired carrier period. 40.7.3 Modulator The modulator block controls the state of the infrared out signal (IRO). The modulator output is gated on to the IRO signal when the modulator/carrier generator is enabled. .
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Functional description When a match is obtained, the cycle repeats by opening the modulator gate, reloading the counter with the contents of CMD1 and CMD2, and reloading the modulation space period register with the contents of CMD3 and CMD4. The modulation space period is activated when the carrier signal is low to prohibit cutting off the high pulse of a carrier signal. If the carrier signal is high, the modulator extends the mark period until the carrier signal becomes low.
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Chapter 40 Carrier Modulator Transmitter (CMT) • The modulation mark period consists of an integer number of (CMTCLK ÷ 8) clock periods. • The modulation space period consists of 0 or an integer number of (CMTCLK ÷ 8) clock periods. With an 8 MHz IF and MSC[CMTDIV] = 00, the modulator resolution is 1 μs and has a maximum mark and space period of about 65.535 ms each . See Figure 40-17 for an example of the Time and Baseband mode outputs.
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Functional description In this mode, the modulator output will be at a logic 1 for the duration of the mark period and at a logic 0 for the duration of a space period. See Figure 40-17 for an example of the output for both Baseband and Time modes. In the example, the carrier out frequency (fcg) is generated with a high count of 0x01 and a low count of 0x02 that results in a divide of 3 of CMTCLK with a 33% duty cycle.
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Chapter 40 Carrier Modulator Transmitter (CMT) • Secondary carrier high count = 0x03 • Secondary carrier low count = 0x01 Carrier out (fcg) Modulator gate Mark1 Space1 Space2 Mark2 Mark1 Space1 Mark2 IRO signal Figure 40-18. Example: CMT output in FSK mode 40.7.4 Extended space operation In either Time, Baseband, or FSK mode, the space period can be made longer than the maximum possible value of the space period register.
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Functional description Set EXSPC Clear EXSPC Figure 40-19. Extended space operation 40.7.4.2 EXSPC operation in FSK mode In FSK mode, the modulator continues to count carrier out clocks, alternating between the primary and secondary registers at the end of each modulation period.
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Chapter 40 Carrier Modulator Transmitter (CMT) 40.8 CMT interrupts and DMA The CMT generates an interrupt request or a DMA transfer request according to MSC[EOCIE], MSC[EOCF], DMA[DMA] bits. Table 40-23. DMA transfer request x CMT interrupt request MSC[EOCF] DMA[DMA] MSC[EOCIE] DMA transfer request CMT interrupt request 0 X X 0 0 1 X 0 0 0 1 0 1 0 1 1 1 1 1 0 MSC[EOCF] is set: • When the modulator is not currently active and MSC[MCGEN] is set to begin the initial CMT transmission.
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CMT interrupts and DMA • Loading the down-counter with the contents of CMD1:CMD2 • Loading the space period register with the contents of CMD3:CMD4 The EOC interrupt provides a means for the user to reload new mark/space values into the modulator data registers. Modulator data register updates will take effect at the end of the current modulation cycle.
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Chapter 41 Real Time Clock (RTC) 41.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. 41.1.1 Features The RTC module features include: • Independent power supply, POR, and 32 kHz crystal oscillator • 32-bit seconds counter with roll-over protection and 32-bit alarm • 16-bit prescaler with compensation that can correct errors between 0.
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Register definition During chip power-down, RTC is powered from the backup power supply (VBAT) and is electrically isolated from the rest of the chip but continues to increment the time counter (if enabled) and retain the state of the RTC registers. The RTC registers are not accessible. During chip power-up, RTC remains powered from the backup power supply (VBAT). All RTC registers are accessible by software and all functions are operational. If enabled, the 32.
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Chapter 41 Real Time Clock (RTC) Write accesses to any register by non-supervisor mode software, when the supervisor access bit in the control register is clear, will terminate with a bus error. Read accesses by non-supervisor mode software complete as normal. Writing to a register protected by the write access register or lock register does not generate a bus error, but the write will not complete.
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Register definition 41.2.2 RTC Time Prescaler Register (RTC_TPR) Address: 4003_D000h base + 4h offset = 4003_D004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TPR W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_TPR field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 41 Real Time Clock (RTC) RTC_TCR field descriptions Field Description 31–24 CIC Compensation Interval Counter 23–16 TCV Time Compensation Value 15–8 CIR Compensation Interval Register 7–0 TCR Time Compensation Register Current value of the compensation interval counter. If the compensation interval counter equals zero then it is loaded with the contents of the CIR. If the CIC does not equal zero then it is decremented once a second.
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Register definition 41.2.
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Chapter 41 Real Time Clock (RTC) RTC_CR field descriptions (continued) Field Description 0 1 Disable the load. Enable the additional load. 10 SC16P Oscillator 16pF Load Configure 9 CLKO Clock Output 8 OSCE Oscillator Enable 7–4 Reserved 3 UM 0 1 0 1 0 1 Disable the load. Enable the additional load. The 32 kHz clock is output to other peripherals. The 32 kHz clock is not output to other peripherals. 32.768 kHz oscillator is disabled. 32.768 kHz oscillator is enabled.
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Register definition 41.2.6 RTC Status Register (RTC_SR) Address: 4003_D000h base + 14h offset = 4003_D014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TAF TOF TIF 0 0 0 1 0 R TCE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 RTC_SR field descriptions Field 31–5 Reserved 4 TCE Description This field is reserved.
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Chapter 41 Real Time Clock (RTC) 41.2.7 RTC Lock Register (RTC_LR) Address: 4003_D000h base + 18h offset = 4003_D018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 LRL SRL CRL TCL 1 1 1 1 1 0 R W Reset 0 0 0 0 0 0 0 0 1 1 1 1 RTC_LR field descriptions Field Description 31–8 Reserved This field is reserved.
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Register definition 41.2.8 RTC Interrupt Enable Register (RTC_IER) Address: 4003_D000h base + 1Ch offset = 4003_D01Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSIE Reserved W TAIE TOIE TIIE 0 0 1 1 1 0 R Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 RTC_IER field descriptions Field Description 31–8 Reserved This field is reserved.
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Chapter 41 Real Time Clock (RTC) 41.2.
PAGE 1022
Register definition RTC_WAR field descriptions (continued) Field Description 0 1 2 TARW Writes to the Time Compensation Register are ignored. Writes to the Time Compensation Register complete as normal. Time Alarm Register Write After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset. 0 1 1 TPRW Writes to the Time Alarm Register are ignored. Writes to the Time Alarm Register complete as normal.
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Chapter 41 Real Time Clock (RTC) RTC_RAR field descriptions (continued) Field Description After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset. 0 1 5 SRR Status Register Read After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset. 0 1 4 CRR After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
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Functional description 41.3.1 Power, clocking, and reset The RTC is an always powered block that remains active in all low power modes and is powered by the battery power supply (VBAT). The battery power supply ensures that the RTC registers retain their state during chip power-down and that the RTC time counter remains operational. The time counter within the RTC is clocked by a 32.768 kHz clock and can supply this clock to other peripherals. The 32.
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Chapter 41 Real Time Clock (RTC) 41.3.1.3 Supervisor access When the supervisor access control bit is clear, only supervisor mode software can write to the RTC registers, non-supervisor mode software will generate a bus error. Both supervisor and non-supervisor mode software can always read the RTC registers. 41.3.2 Time counter The time counter consists of a 32-bit seconds counter that increments once every second and a 16-bit prescaler register that increments once every 32.768 kHz clock cycle.
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Functional description Crystal compensation can be supported by using firmware and crystal characteristics to determine the compensation amount. Temperature compensation can be supported by firmware that periodically measures the external temperature via ADC and updates the compensation register based on a look-up table that specifies the change in crystal frequency over temperature. The compensation logic alters the number of 32.
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Chapter 41 Real Time Clock (RTC) time seconds and prescaler registers to be initialized whenever time is invalidated, while preventing the time seconds and prescaler registers from being changed on the fly. When LR[SRL] is set, CR[UM] has no effect on SR[TCE]. 41.3.6 Register lock The lock register can be used to block write accesses to certain registers until the next VBAT POR or software reset. Locking the control register will disable the software reset.
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Functional description K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 1028 Preliminary General Business Information Freescale Semiconductor, Inc.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. This section describes the USB. The OTG implementation in this module provides limited host functionality and device solutions for implementing a USB 2.0 full-speed/ low-speed compliant peripheral. The OTG implementation supports the On-The-Go (OTG) addendum to the USB 2.0 Specification.
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Introduction The host initiates transactions to specific peripherals, whereas the device responds to control transactions. The device sends and receives data to and from the host using a standard USB data format. USB 2.0 full-speed /low-speed peripherals operate at 12Mbit/s or 1.5 Mbit/s. For additional information, see the USB 2.0 specification. Host PC External Hub External Hub Root Hub Host Software USB Cable USB Cable USB Cables USB Cable USB Peripherals Figure 42-1. Example USB 2.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) Print Photos Keyboard Input Swap Songs Hot Sync Figure 42-2. Example USB 2.0 On-The-Go configurations 42.1.3 USB-FS Features • USB 1.1 and 2.0 compliant full-speed device controller • 16 bidirectional end points • DMA or FIFO data stream interfaces • Low-power consumption • On-The-Go protocol logic 42.2 External Signal Description K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Functional description 42.3 Functional description The USB-FS 2.0 full-speed/low-speed module communicates with the processor core through status registers, control registers, and data structures in memory. 42.3.1 Data Structures The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus. To efficiently manage USB endpoint communications the USB-FS implements a Buffer Descriptor Table (BDT) in system memory. See Figure 42-3. 42.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) memory when the OWN bit is 0. When the OWN bit is set to 1, the BD entry and the buffer in system memory are owned by the USB-FS. The USB-FS now has full read and write access and the microprocessor must not modify the BD or its corresponding data buffer. The BD also contains indirect address pointers to where the actual buffer resides in system memory. This indirect address mechanism is shown in the following diagram.
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Programmers interface Table 42-1. Data direction for USB host or USB target Device Host RX TX OUT or SETUP IN IN OUT or SETUP 42.4.3 Addressing BDT entries An understanding of the addressing mechanism of the Buffer Descriptor Table is useful when accessing endpoint data via the USB-FS or microprocessor. Some points of interest are: • • • • • • • The BDT occupies up to 512 bytes of system memory. 16 bidirectional endpoints can be supported with a full BDT of 512 bytes.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.4.4 Buffer Descriptors (BDs) A buffer descriptor provides endpoint buffer control information for the USB-FS and processor. The Buffer Descriptors have different meaning based on whether it is the USB-FS or processor reading the BD in memory.
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Programmers interface Table 42-4. Buffer descriptor fields (continued) Field 25–16 BC 15–8 Description Byte Count Represents the 10-bit byte count. The USB-FS SIE changes this field upon the completion of a RX transfer with the byte count of the data received. Reserved RSVD 7 OWN Determines whether the processor or the USB-FS currently owns the buffer. Except when KEEP=1, the SIE hands ownership back to the processor after completing the token by clearing this bit.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) Table 42-4. Buffer descriptor fields (continued) Field TOK_PID[n] Description Bits [5:2] can also represent the current token PID. The current token PID is written back in to the BD by the USB-FS when a transfer completes. The values written back are the token PID values from the USB specification: • 0x1h for an OUT token. • 0x9h for an IN token. • 0xDh for a SETUP token.
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Programmers interface USB RST SOF USB_RST Interrupt Generated SOF Interrupt Generated SETUP TOKEN DATA ACK TOK_DNE Interrupt Generated DATA IN TOKEN ACK TOK_DNE Interrupt Generated OUT TOKEN DATA USB Host ACK TOK_DNE Interrupt Generated Function Figure 42-4. USB token transaction The USB has two sources for the DMA overrun error: Memory Latency The memory latency may be too high and cause the receive FIFO to overflow.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) Table 42-5. USB responses to DMA overrun errors (continued) Errors due to Memory Latency Errors due to Oversized Packets • For host mode, the TOKDNE interrupt is generated and The packet length field written back to the BDT is the the TOK_PID field of the BDT is 1111 to indicate the MaxPacket value that represents the length of the clipped DMA latency error. Host mode software can decide to data actually written to memory.
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Memory map/Register definitions USB memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4007_209C BDT Page Register 1 (USB0_BDTPAGE1) 8 R/W 00h 42.5.16/ 1054 4007_20A0 Frame Number Register Low (USB0_FRMNUML) 8 R/W 00h 42.5.17/ 1054 4007_20A4 Frame Number Register High (USB0_FRMNUMH) 8 R/W 00h 42.5.18/ 1055 4007_20A8 Token register (USB0_TOKEN) 8 R/W 00h 42.5.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USB memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_20FC Endpoint Control register (USB0_ENDPT15) 8 R/W 00h 42.5.23/ 1057 4007_2100 USB Control register (USB0_USBCTRL) 8 R/W C0h 42.5.24/ 1058 4007_2104 USB OTG Observe register (USB0_OBSERVE) 8 R 50h 42.5.25/ 1059 4007_2108 USB OTG Control register (USB0_CONTROL) 8 R/W 00h 42.5.
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Memory map/Register definitions 42.5.2 Peripheral ID Complement register (USBx_IDCOMP) Reads back the complement of the Peripheral ID register. For the USB peripheral, the value is 0xFB. Address: 4007_2000h base + 4h offset = 4007_2004h Bit 7 Read 6 5 4 3 2 1 0 0 1 1 3 2 1 0 0 0 1 1 1 NID Write Reset 1 1 1 1 1 USBx_IDCOMP field descriptions Field 7–6 Reserved 5–0 NID Description This field is reserved. This read-only field is reserved and always has the value 1.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.5.4 Peripheral Additional Info register (USBx_ADDINFO) Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with the Host Enable bit. Address: 4007_2000h base + Ch offset = 4007_200Ch Bit 7 6 5 Read 4 3 2 IRQNUM 1 0 0 IEHOST Write Reset 0 0 0 0 0 0 0 1 USBx_ADDINFO field descriptions Field Description 7–3 IRQNUM Assigned Interrupt Request Number 2–1 Reserved This field is reserved.
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Memory map/Register definitions USBx_OTGISTAT field descriptions (continued) Field 4 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 3 SESSVLDCHG This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid. 2 B_SESS_CHG This bit is set when a change in VBUS is detected on a B device. 1 Reserved 0 AVBUSCHG This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_OTGICR field descriptions (continued) Field Description 0 1 Disables the B_SESS_CHG interrupt. Enables the B_SESS_CHG interrupt. 1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 AVBUSEN A VBUS Valid Interrupt Enable 0 1 Disables the AVBUSCHG interrupt. Enables the AVBUSCHG interrupt. 42.5.
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Memory map/Register definitions USBx_OTGSTAT field descriptions (continued) Field Description 2 BSESSEND B Session End 0 1 1 Reserved The VBUS voltage is above the B session end threshold. The VBUS voltage is below the B session end threshold. This field is reserved. This read-only field is reserved and always has the value 0. 0 AVBUSVLD A VBUS Valid 0 1 The VBUS voltage is below the A VBUS Valid threshold. The VBUS voltage is above the A VBUS Valid threshold. 42.5.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_OTGCTL field descriptions (continued) Field Description 0 1 1–0 Reserved If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D– Data Line pull-down resistors are engaged. The pull-up and pull-down controls in this register are used. This field is reserved. This read-only field is reserved and always has the value 0. 42.5.
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Memory map/Register definitions USBx_ISTAT field descriptions (continued) Field Description In Host mode this field is set when the SOF threshold is reached, so that software can prepare for the next SOF. 1 ERROR This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register to determine the source of the error. 0 USBRST This bit is set when the USB Module has decoded a valid USB reset.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_INTEN field descriptions (continued) Field Description 0 1 Disbles the SOFTOK interrupt. Enables the SOFTOK interrupt. 1 ERROREN ERROR Interrupt Enable 0 USBRSTEN USBRST Interrupt Enable 0 1 0 1 Disables the ERROR interrupt. Enables the ERROR interrupt. Disables the USBRST interrupt. Enables the USBRST interrupt. 42.5.
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Memory map/Register definitions USBx_ERRSTAT field descriptions (continued) Field Description OUT TOKEN or the data and handshake phases of a IN TOKEN. If more than 16 bit times are counted from the previous EOP before a transition from IDLE, a bus turnaround timeout error occurs. 3 DFN8 2 CRC16 1 CRC5EOF This bit is set if the data field received was not 8 bits in length. USB Specification 1.0 requires that data fields be an integral number of bytes.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_ERREN field descriptions (continued) Field 4 BTOERREN 3 DFN8EN 2 CRC16EN 1 CRC5EOFEN 0 PIDERREN Description BTOERR Interrupt Enable 0 1 Disables the BTOERR interrupt. Enables the BTOERR interrupt. DFN8 Interrupt Enable 0 1 Disables the DFN8 interrupt. Enables the DFN8 interrupt. CRC16 Interrupt Enable 0 1 Disables the CRC16 interrupt. Enables the CRC16 interrupt. CRC5/EOF Interrupt Enable 0 1 Disables the CRC5/EOF interrupt.
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Memory map/Register definitions USBx_STAT field descriptions Field Description 7–4 ENDP This four-bit field encodes the endpoint address that received or transmitted the previous token. This allows the processor core to determine the BDT entry that was updated by the last USB transaction. 3 TX Transmit Indicator 0 1 2 ODD The most recent transaction was a receive operation. The most recent transaction was a transmit operation.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_CTL field descriptions (continued) Field Description 3 HOSTMODEEN When set to 1, this bit enables the USB Module to operate in Host mode. In host mode, the USB module performs USB transactions under the programmed control of the host processor. 2 RESUME When set to 1 this bit enables the USB Module to execute resume signaling. This allows the USB Module to perform remote wake-up.
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Memory map/Register definitions 42.5.16 BDT Page Register 1 (USBx_BDTPAGE1) Provides address bits 15 through 9 of the base address where the current Buffer Descriptor Table (BDT) resides in system memory. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so bits 8 through 0 of the base address are always zero.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.5.18 Frame Number Register High (USBx_FRMNUMH) Contains an 11-bit value used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory. Address: 4007_2000h base + A4h offset = 4007_20A4h Bit Read Write Reset 7 6 5 4 3 2 0 0 0 0 1 0 FRM[10:8] 0 0 0 0 0 USBx_FRMNUMH field descriptions Field Description 7–3 Reserved This field is reserved.
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Memory map/Register definitions USBx_TOKEN field descriptions (continued) Field Description 0001 1001 1101 3–0 TOKENENDPT OUT Token. USB Module performs an OUT (TX) transaction. IN Token. USB Module performs an In (RX) transaction. SETUP Token. USB Module performs a SETUP (TX) transaction Holds the Endpoint address for the token command. The four bit value written must be a valid endpoint. 42.5.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.5.21 BDT Page Register 2 (USBx_BDTPAGE2) Contains an 8-bit value used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory.
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Memory map/Register definitions In Host mode ENDPT0 is used to determine the handshake, retry and low speed characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK bit should be 1. For Isochronous transfers it should be 0. Common values to use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, and 0x4C for Isochronous transfers.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_USBCTRL field descriptions Field 7 SUSP 6 PDE 5–0 Reserved Description Places the USB transceiver into the suspend state. 0 1 USB transceiver is not in suspend state. USB transceiver is in suspend state. Enables the weak pulldowns on the USB transceiver. 0 1 Weak pulldowns are disabled on D+ and D–. Weak pulldowns are enabled on D+ and D–. This field is reserved. This read-only field is reserved and always has the value 0. 42.5.
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Memory map/Register definitions 42.5.26 USB OTG Control register (USBx_CONTROL) Address: 4007_2000h base + 108h offset = 4007_2108h Bit 7 6 5 0 4 Read Write Reset 0 0 0 0 Bit 3 2 1 0 0 0 Read Write Reset DPPULLUPNONOTG 0 0 0 USBx_CONTROL field descriptions Field Description 7–5 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) USBx_USBTRC0 field descriptions (continued) Field Description NOTE: This bit is always read as zero. Wait two USB clock cycles after setting this bit. 0 1 6 Reserved 5 USBRESMEN This field is reserved. This read-only field is reserved and always has the value 0. Asynchronous Resume Interrupt Enable This bit, when set, allows the USB module to send an asynchronous wakeup event to the MCU upon detection of resume signaling on the USB bus.
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OTG and Host mode operation 42.6 OTG and Host mode operation The Host mode logic allows devices such as digital cameras and palmtop computers to function as a USB Host Controller. The OTG logic adds an interface to allow the OTG Host Negotiation and Session Request Protocols (HNP and SRP) to be implemented in software. Host Mode allows a peripheral such as a digital camera to be connected directly to a USB compliant printer. Digital photos can then be easily printed without having to upload them to a PC.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 2. Enable the ATTACH interrupt (INT_ENB[ATTACH]=1). 3. Wait for ATTACH interrupt (INT_STAT[ATTACH]). Signaled by USB Target pullup resistor changing the state of DPLUS or DMINUS from 0 to 1 (SE0 to J or K state). 4. Check the state of the JSTATE and SE0 bits in the control register.
PAGE 1064
Host Mode Operation Examples complete. When the BDT is written, a token done (ISTAT[TOKDNE]) interrupt is asserted. This completes the setup phase of the setup transaction. Se the Universal Serial Bus Revision 2.0 specification, "Chapter 9 USB Device Framework" (http:// www.usb.org/developers/docs). 7. To initiate the data phase of the setup transaction (that is, get the data for the GET DEVICE DESCRIPTOR command), set up a buffer in memory for the data to be transferred. 8.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 1. Complete all steps to discover a connected device and to configure a connected device. Write the ADDR register with the address of the target device. Typically, there is only one other device on the USB bus in host mode so it is expected that the address is 0x01 and should remain constant. 2. Write 0x1D to ENDPT0 register to enable transmit and receive transfers with handshaking enabled. 3. Setup the even TX EP0 BDT to transfer up to 64 bytes. 4.
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On-The-Go operation 42.8.1 OTG dual role A device operation A device is considered the A device because of the type of cable attached. If the USB Type A connector or the USB Type Mini A connector is plugged into the device, it is considered the A device. A dual role A device operates as the following flow diagram and state description table illustrates. A_IDLE B_IDLE A_WAIT_VFALL A_WAIT_VRISE A_PERIPHERAL A_WAIT_BCON A_SUSPEND A_HOST Figure 42-93. Dual role A device flow diagram Table 42-96.
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Chapter 42 Universal Serial Bus OTG Controller (USBOTG) Table 42-96. State descriptions for the dual role A device flow (continued) State Action Response A_WAIT_BCON After 200 ms without Attach or ID Interrupt. (This could wait forever if desired.) Go to A_WAIT_FALL A_VBUS_VLD Interrupt and B device attaches Go to A_HOST Turn off DRV_VBUS Turn on Host mode A_HOST Enumerate Device determine OTG Support.
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On-The-Go operation B_IDLE A_IDLE B_HOST B_SRP_INIT B_WAIT_ACON B_PERIPHERAL Figure 42-94. Dual role B device flow diagram Table 42-97. State descriptions for the dual role B device flow State Action Response B_IDLE If ID\ Interrupt. Go to A_IDLE A Type A cable has been plugged in and the device should now respond as a Type A device. If B_SESS_VLD Interrupt. Go to B_PERIPHERAL The A device has turned on VBUS and begins a session.
PAGE 1069
Chapter 42 Universal Serial Bus OTG Controller (USBOTG) 42.9 Hardware Interface 42.9.1 Figure 42-95. 42.10 System Level Issues and Configuration 42.10.1 42.10.2 Power The USB-FS core is a fully synchronous static design. The power used by the design is dependant on the application usage of the core. Applications that transfer more data or cause a greater number of packets to be sent consumes a greater amount of power.
PAGE 1070
System Level Issues and Configuration maximum USB bus power budget of 500 uA. To achieve that level of power conservation, most of the device circuits need to be switched off. When the clock is disabled to the USB-FScore all functions are disabled, but all operational states are retained.
PAGE 1071
Chapter 43 USB Device Charger Detection Module (USBDCD) 43.1 Preface 43.1.1 References The following publications are referenced in this document. For updates to these specifications, see http://www.usb.org. • USB Battery Charging Specification Revision 1.1, USB Implementers Forum • Universal Serial Bus Specification Revision 2.0, USB Implementers Forum 43.1.2 Acronyms and abbreviations The following table contains acronyms and abbreviations used in this document. Table 43-1.
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Introduction Table 43-1. Acronyms and abbreviated terms (continued) Term Meaning RDM_DWN D– pulldown resistance for data pin contact detect VDAT_REF Data detect reference voltage for the voltage comparator VDP_SRC Voltage source for the D+ line VLGC Threshold voltage for logic high 43.1.3 Glossary The following table shows a glossary of terms used in this document. Table 43-2.
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Chapter 43 USB Device Charger Detection Module (USBDCD) clk reset Digital Block Bus interface & registers Analog Block Timer Unit Voltage Comparator bus Control and Feedback state of D– Current Sink D+ D D– state of D+ Analog Control Unit D– pulldown enable Current Source Voltage Source Figure 43-1. Block diagram The USBDCD module consists of two main blocks: • A digital block provides the programming interface (memory-mapped registers) and includes the timer unit and the analog control unit.
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Module signal descriptions Table 43-3. Module modes and their conditions Module mode Description Conditions when used Enabled The module performs the charger detection sequence. System software should enable the module only when all of the following conditions are true: Disabled Powered Off The module is not active and is held in a low power state. The digital supply voltage dvdd is removed. • The system uses a rechargeable battery. • The device is being used in an FS USB device application.
PAGE 1075
Chapter 43 USB Device Charger Detection Module (USBDCD) Table 43-5. Signal descriptions Signal Description I/O usb_dm USB D– analog data signal. The analog block interfaces directly to the D– signal on the USB bus. I/O usb_dp USB D+ analog data signal. The analog block interfaces directly to the D+ signal on the USB bus. I/O avdd331 3.3 V regulated analog supply I avss Analog ground I dvss Digital ground I dvdd 1.2 V digital supply I 1. Voltage must be 3.
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Memory map/Register definition 43.4.1 Control register (USBDCD_CONTROL) Contains the control and interrupt bit fields.
PAGE 1077
Chapter 43 USB Device Charger Detection Module (USBDCD) USBDCD_CONTROL field descriptions (continued) Field Description 0 1 15–9 Reserved Disable interrupts to the system. Enable interrupts to the system. This field is reserved. 8 IF Interrupt Flag Determines whether an interrupt is pending. 0 1 7–1 Reserved No interrupt is pending. An interrupt is pending. This field is reserved. This read-only field is reserved and always has the value 0.
PAGE 1078
Memory map/Register definition USBDCD_CLOCK field descriptions (continued) Field Description The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples with CLOCK_UNIT = 1: • For 48 MHz: 0b00_0011_0000 (48) (Default) • For 24 MHz: 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: • For 100 kHz: 0b00_0110_0100 (100) • For 500 kHz: 0b01_1111_0100 (500) 1 Reserved 0 CLOCK_UNIT This field is reserved.
PAGE 1079
Chapter 43 USB Device Charger Detection Module (USBDCD) 43.4.3 Status register (USBDCD_STATUS) Provides the current state of the module for system software monitoring.
PAGE 1080
Memory map/Register definition USBDCD_STATUS field descriptions (continued) Field Description 0 1 20 ERR Error Flag Indicates whether there is an error in the detection sequence. 0 1 19–18 SEQ_STAT Indicates the status of the charger detection sequence. 01 10 11 The module is either not enabled, or the module is enabled but the data pins have not yet been detected. Data pin contact detection is complete. Charging port detection is complete. Charger type detection is complete.
PAGE 1081
Chapter 43 USB Device Charger Detection Module (USBDCD) Address: 4003_5000h base + 10h offset = 4003_5010h Bit 31 30 29 28 27 26 25 24 23 0 R 0 0 0 21 20 19 18 17 16 15 14 0 0 0 0 0 0 0 0 1 0 13 12 11 10 9 8 0 TSEQ_INIT W Reset 22 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 TUNITCON 0 0 0 0 0 0 0 0 0 0 USBDCD_TIMER0 field descriptions Field Description 31–26 Reserved This field is reserved.
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Memory map/Register definition USBDCD_TIMER1 field descriptions (continued) Field Description 25–16 TDCD_DBNC Time Period to Debounce D+ Signal Sets the time period (ms) to debounce the D+ signal during the data pin contact detection phase. See "Debouncing the data pin contact" Valid values are 1–1023, but the USB Battery Charging Specification requires a minimum value of 10 ms. 15–10 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
PAGE 1083
Chapter 43 USB Device Charger Detection Module (USBDCD) 43.5 Functional description The sequence of detecting the presence of charging port and type of charging port involves several hardware components, coordinated by system software. This collection of interacting hardware and software is called the USB Battery Charging Subsystem. The following figure shows the USBDCD module as a component of the subsystem. The following table describes the components.
PAGE 1084
Functional description Table 43-13. USB battery charger subsystem components (continued) Component USB Transceiver Description The USB transceiver contains the pullup resistor for the USB D+ signal and the pulldown resistors for the USB D+ and D– signals. The D+ pullup and the D– pulldown are both used during the charger detection sequence. The USB transceiver also outputs the digital state of the D+ and D– signals from the USB bus.
PAGE 1085
Chapter 43 USB Device Charger Detection Module (USBDCD) 1 2 Initial VBUS Conditions Detect Charger Detection Phase 3 4 5 6 Data Pin Contact Detection Charging Port Detection Charger Type Detection Timeout T UNIT_CON_ELAPSED = T SEQ_INIT T UNIT_CON_ELAPSED =1s V B U S a t p o rta b le U S B d e v ice I DEV_DCHG D e d ic a te d C h a rg e r C h a rg in g H o s t T SEQ_INIT Dedicated Charger C h a rg in g H o s t I DEV_HCHG_LFS I SUSP 0m A I DP_SRC R DM_DWN FullSpeed Portable USB Device D+
PAGE 1086
Functional description Table 43-14. Overview of the charger detection sequence Phase Overview description Full description Initial System Conditions 1 Initial Conditions Initial system conditions that need to be met before the detection sequence is initiated. 2 VBUS Detection System software detects contact of the VBUS signal with the system interrupt pin VBUS contact VBUS_detect.
PAGE 1087
Chapter 43 USB Device Charger Detection Module (USBDCD) Examples of allowable precursors to this set of initial conditions include: • A powered-down device is subsequently powered-up upon being plugged into the USB bus. • A device in a low power mode subsequently enters run mode upon being plugged into the USB bus. 43.5.1.2 VBUS contact detection Once the device is plugged into a USB port, the VBUS_detect system interrupt is triggered.
PAGE 1088
Functional description As a result, when a portable USB device is attached to an upstream port, the portable USB device detects VBUS before the data pins have made contact. The time between power pins and data pins making contact depends on how fast the plug is inserted into the receptable. Delays of several hundred milliseconds are possible. 43.5.1.3.
PAGE 1089
Chapter 43 USB Device Charger Detection Module (USBDCD) 43.5.1.4 Charging port detection After it detects that the data pins have made contact, the module waits for a fixed delay of 1 ms, and then attempts to detect whether it is plugged into a charging port.
PAGE 1090
Functional description 1. Read the STATUS register. 2. Set CONTROL[IACK] to acknowledge the interrupt. 3. Set CONTROL[SR] to issue a software reset to the module. 4. Disable the module. 5. Communicate the appropriate charge rate to the external battery charger IC; see Table 43-13. 43.5.1.4.
PAGE 1091
Chapter 43 USB Device Charger Detection Module (USBDCD) At this point, control has been passed to system software via the interrupt. The rest of the sequence (detecting the type of charging port) is not applicable, so software should: 1. Read the STATUS register. 2. Set CONTROL[IACK] to acknowledge the interrupt. 3. Set CONTROL[SR] to issue a software reset to the module. 4. Disable the module. 43.5.1.
PAGE 1092
Functional description 2. Disable the USB controller to prevent transitions on the USB D+ or D– lines from causing spurious interrupt or wakeup events to the system. 3. Set CONTROL[IACK] to acknowledge the interrupt. 4. Set CONTROL[SR] to issue a software reset to the module. 5. Disable the module. 6. Communicate the appropriate charge rate to the external battery charger IC; see Table 43-13. 43.5.1.5.
PAGE 1093
Chapter 43 USB Device Charger Detection Module (USBDCD) • Updates the STATUS register to reflect that a timeout error has occured. See Table 43-18 for field values. • Sets the CONTROL[IF] bit. • Generates an interrupt if enabled in CONTROL[IE]. • The detection sequence continues until explicitly halted by software setting the CONTROL[SR] bit. • The Unit Connection Timer continues counting. See the description of the TIMER0 Register.
PAGE 1094
Functional description 43.5.2 Interrupts and events The USBDCD module has an interrupt to alert system software of certain events, which are listed in the following table. All events except the Phase Complete event for the Data Pin Detection phase can trigger an interrupt. Table 43-18. Events triggering an interrupt by sequence phase Sequence phase Event Event description STATUS fields1 Data Pin Detection Phase Complete The module has detected data pin contact.
PAGE 1095
Chapter 43 USB Device Charger Detection Module (USBDCD) Writes to CONTROL[IF] are ignored. To reset CONTROL[IF], set CONTROL[IACK] to acknowledge the interrupt. Writing to CONTROL[IACK] when CONTROL[IF] is cleared has no effect. 43.5.3 Resets There are two ways to reset various register contents in this module: hardware resets and a software reset. 43.5.3.1 Hardware resets Hardware resets originate at the system or device level and propagate down to the individual module level.
PAGE 1096
Initialization information Note Software must always initiate a software reset before starting the sequence to ensure the module is in a known state. 43.6 Initialization information This module has been designed for minimal configuration while retaining significant programmability. The CLOCK register needs to be initialized to the actual system clock frequency, unless the default value already matches the system requirements.
PAGE 1097
Chapter 43 USB Device Charger Detection Module (USBDCD) The module is also compatible with systems that do check the strength of the battery. In these systems, if it is known that the battery is weak or dead, software can delay connecting to the USB while charging at 1.5A. Once the battery is charged to the good battery threshold, software can then connect to the USB host by pulling the D+ line high. 43.7.
PAGE 1098
Application information K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 1098 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 1099
Chapter 44 USB Voltage Regulator 44.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The USB Voltage Regulator module is a LDO linear voltage regulator to provide 3.3V power from an input power supply varying from 2.7 V to 5.5 V. It consists of one 3.3 V power channel. When the input power supply is below 3.6 V, the regulator goes to passthrough mode.
PAGE 1100
Introduction 44.1.1 Overview A simplified block diagram for the USB Voltage Regulator module is shown below. STANDBY Regulator Yes No Other Modules STANDBY Power Supply reg33_in Regulated Output Voltage reg33_out RUN Regulator ESR: 5m -> 100m Ohms Voltage Regulator External Capacitor typical = 2.2uF Chip Figure 44-2. USB Voltage Regulator Block Diagram This module uses 2 regulators in parallel.
PAGE 1101
Chapter 44 USB Voltage Regulator • Automatic current limiting if the load current is greater than 290 mA. • Automatic power-up once some voltage is applied to the regulator input. • Pass-through mode for regulator input voltages less than 3.6 V • Small output capacitor: 2.2 uF • Stable with aluminum, tantalum or ceramic capacitors. 44.1.
PAGE 1102
USB Voltage Regulator Module Signal Descriptions K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 1102 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 1103
Chapter 45 CAN (FlexCAN) 45.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The FlexCAN module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification.
PAGE 1104
Introduction Peripheral Bus Interface Address, Data, Clocks, Interrupts Registers Message Buffers (MBs) CAN Control Host Interface Tx Arbitration Rx Matching RAM CAN Protocol Engine CAN Tx CAN Rx Chip CAN Transceiver CAN Bus Figure 45-1. FlexCAN block diagram 45.1.
PAGE 1105
Chapter 45 CAN (FlexCAN) 45.1.2 FlexCAN module features The FlexCAN module includes these distinctive legacy features: • Full implementation of the CAN protocol specification, Version 2.
PAGE 1106
Introduction • Short latency time due to an arbitration scheme for high-priority messages • Low power modes, with programmable wake up on bus activity New major features are also provided: • Remote request frames may be handled automatically or by software • CAN bit time settings and configuration bits can only be written in Freeze mode • Tx mailbox status (Lowest priority buffer or empty buffer) • IDHIT register for received frames • SYNC bit status to inform that the module is synchronous with CAN bus •
PAGE 1107
Chapter 45 CAN (FlexCAN) • Listen-Only mode: The module enters this mode when the LOM bit in the Control 1 Register is asserted. In this mode, transmission is disabled, all error counters are frozen and the module operates in a CAN Error Passive mode. Only messages acknowledged by another CAN station will be received. If FlexCAN detects a message that has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the message.
PAGE 1108
FlexCAN signal descriptions 45.2 FlexCAN signal descriptions The FlexCAN module has two I/O signals connected to the external MCU pins. These signals are summarized in the following table and described in more detail in the next sub-sections. Table 45-1. FlexCAN signal descriptions Signal Description I/O CAN Rx CAN Receive Pin Input CAN Tx CAN Transmit Pin Output 45.2.1 CAN Rx This pin is the receive pin from the CAN bus transceiver. Dominant state is represented by logic level 0.
PAGE 1109
Chapter 45 CAN (FlexCAN) Each individual register is identified by its complete name and the corresponding mnemonic. The access type can be Supervisor (S) or Unrestricted (U). Most of the registers can be configured to have either Supervisor or Unrestricted access by programming the SUPV bit in the MCR Register. These registers are identified as S/U in the Access column of Table 45-2. Table 45-2.
PAGE 1110
Memory map/register definition CAN memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_4000 Module Configuration Register (CAN0_MCR) 32 R/W D890_000Fh 45.3.2/1112 4002_4004 Control 1 register (CAN0_CTRL1) 32 R/W 0000_0000h 45.3.3/1117 4002_4008 Free Running Timer (CAN0_TIMER) 32 R/W 0000_0000h 45.3.4/1120 4002_4010 Rx Mailboxes Global Mask Register (CAN0_RXMGMASK) 32 R/W FFFF_FFFFh 45.3.
PAGE 1111
Chapter 45 CAN (FlexCAN) CAN memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page Rx Individual Mask Registers (CAN0_RXIMR10) 32 R/W Undefined 45.3.17/ 1139 4002_48AC Rx Individual Mask Registers (CAN0_RXIMR11) 32 R/W Undefined 45.3.17/ 1139 4002_48B0 Rx Individual Mask Registers (CAN0_RXIMR12) 32 R/W Undefined 45.3.17/ 1139 4002_48B4 Rx Individual Mask Registers (CAN0_RXIMR13) 32 R/W Undefined 45.3.
PAGE 1112
Memory map/register definition 45.3.2 Module Configuration Register (CANx_MCR) This register defines global system configurations, such as the module operation modes and the maximum message buffer configuration.
PAGE 1113
Chapter 45 CAN (FlexCAN) CANx_MCR field descriptions (continued) Field Description 0 1 29 RFEN Rx FIFO Enable This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is set, MBs 0 to 5 cannot be used for normal reception and transmission because the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used as Rx FIFO ID Filter Table elements.
PAGE 1114
Memory map/register definition CANx_MCR field descriptions (continued) Field 24 FRZACK Description Freeze Mode Acknowledge This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler is stopped. The Freeze mode request cannot be granted until current transmission or reception processes have finished. Therefore the software can poll the FRZACK bit to know when FlexCAN has actually entered Freeze mode.
PAGE 1115
Chapter 45 CAN (FlexCAN) CANx_MCR field descriptions (continued) Field Description NOTE: LPMACK will be asserted within 180 CAN bits from the low-power mode request by the CPU, and negated within 2 CAN bits after the low-power mode request removal (see Section "Protocol Timing"). 0 1 19 WAKSRC FlexCAN is not in a low-power mode. FlexCAN is in a low-power mode. Wake Up Source This bit defines whether the integrated low-pass filter is applied to protect the Rx CAN input from spurious wake up.
PAGE 1116
Memory map/register definition CANx_MCR field descriptions (continued) Field Description NOTE: When MCR[AEN] is asserted, only the abort mechanism (see Section "Transmission Abort Mechanism") must be used for updating Mailboxes configured for transmission. CAUTION: Writing the Abort code into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is asserted. 0 1 11–10 Reserved 9–8 IDAM This field is reserved. This read-only field is reserved and always has the value 0.
PAGE 1117
Chapter 45 CAN (FlexCAN) 45.3.3 Control 1 register (CANx_CTRL1) This register is defined for specific FlexCAN control features related to the CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling (Bus-Off, Error, Warning). It also determines the Division Factor for the clock prescaler.
PAGE 1118
Memory map/register definition CANx_CTRL1 field descriptions (continued) Field Description This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time. The valid programmable values are 1–7. This field can be written only in Freeze mode because it is blocked by hardware in other modes. Phase Buffer Segment 2 = (PSEG2 + 1) × Time-Quanta. 15 BOFFMSK Bus Off Mask This bit provides a mask for the Bus Off Interrupt.
PAGE 1119
Chapter 45 CAN (FlexCAN) CANx_CTRL1 field descriptions (continued) Field Description This bit provides a mask for the Rx Warning Interrupt associated with the RWRNINT flag in the Error and Status Register. This bit is read as zero when MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is asserted. 0 1 9–8 Reserved 7 SMP This field is reserved. This read-only field is reserved and always has the value 0.
PAGE 1120
Memory map/register definition CANx_CTRL1 field descriptions (continued) Field Description acknowledged by another CAN station will be received. If FlexCAN detects a message that has not been acknowledged, it will flag a BIT0 error without changing the REC, as if it was trying to acknowledge the message. Listen-Only mode acknowledgement can be obtained by the state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is entered.
PAGE 1121
Chapter 45 CAN (FlexCAN) Address: 4002_4000h base + 8h offset = 4002_4008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TIMER W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CANx_TIMER field descriptions Field Description 31–16 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
PAGE 1122
Memory map/register definition CANx_RXMGMASK field descriptions (continued) Field Description SMB[RTR]1 CTRL2[RRS] CTRL2[EACE N] Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved note3 MG[28:0] MG[31:29] 0 - 0 note2 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - - MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29] 1. RTR bit of the Incoming Frame. It is saved into an auxiliary MB called Rx Serial Message Buffer (Rx SMB). 2.
PAGE 1123
Chapter 45 CAN (FlexCAN) CANx_RX14MASK field descriptions (continued) Field Description 0 1 The corresponding bit in the filter is "don’t care." The corresponding bit in the filter is checked. 45.3.7 Rx 15 Mask register (CANx_RX15MASK) This register is located in RAM. RX15MASK is provided for legacy application support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK is used to mask the filter fields of Message Buffer 15.
PAGE 1124
Memory map/register definition The following are the basic rules for FlexCAN bus state transitions: • If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to 128, the FLTCONF field in the Error and Status Register is updated to reflect ‘Error Passive’ state.
PAGE 1125
Chapter 45 CAN (FlexCAN) CANx_ECR field descriptions (continued) Field Description 7–0 TXERRCNT Transmit Error Counter 45.3.9 Error and Status 1 register (CANx_ESR1) This register reflects various error conditions, some general status of the device and it is the source of interrupts to the CPU. The CPU read action clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those that occurred since the last time the CPU read this register. Bits 9-3 are status bits.
PAGE 1126
13 12 11 10 9 8 7 6 R BIT0ERR ACKERR CRCERR FRMERR STFERR TXWRN RXWRN IDLE TX 5 4 FLTCONF 3 RX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 WAKINT 14 ERRINT 15 BOFFINT Bit BIT1ERR Memory map/register definition w1c w1c w1c 0 0 0 CANx_ESR1 field descriptions Field 31–19 Reserved 18 SYNCH Description This field is reserved. This read-only field is reserved and always has the value 0.
PAGE 1127
Chapter 45 CAN (FlexCAN) CANx_ESR1 field descriptions (continued) Field Description NOTE: This bit is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node sending a passive error flag that detects dominant bits. 0 1 14 BIT0ERR Bit0 Error This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message.
PAGE 1128
Memory map/register definition CANx_ESR1 field descriptions (continued) Field Description 0 1 7 IDLE This bit indicates when CAN bus is in IDLE state. See the table in the overall CAN_ESR1 register description. 0 1 6 TX No such occurrence. CAN bus is now IDLE. FlexCAN In Transmission This bit indicates if FlexCAN is transmitting a message. See the table in the overall CAN_ESR1 register description. 0 1 5–4 FLTCONF No such occurrence. RXERRCNT is greater than or equal to 96.
PAGE 1129
Chapter 45 CAN (FlexCAN) CANx_ESR1 field descriptions (continued) Field Description This field applies when FlexCAN is in low-power mode: • Stop mode When a recessive-to-dominant transition is detected on the CAN bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag is masked. The CPU must clear this flag before disabling the bit. Otherwise it will be set when the SLFWAK is set again.
PAGE 1130
Memory map/register definition 45.3.11 Interrupt Flags 1 register (CANx_IFLAG1) This register defines the flags for the 32 Message Buffer interrupts for MB31 to MB0. It contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding IFLAG1 bit. If the corresponding IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be cleared by writing 1 to it. Writing 0 has no effect.
PAGE 1131
Chapter 45 CAN (FlexCAN) CANx_IFLAG1 field descriptions Field 31–8 BUF31TO8I Description Buffer MBi Interrupt Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to MB8. 0 1 7 BUF7I The corresponding buffer has no occurrence of successfully completed transmission or reception. The corresponding buffer has successfully completed transmission or reception.
PAGE 1132
Memory map/register definition CANx_IFLAG1 field descriptions (continued) Field Description 0 1 The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. 45.3.12 Control 2 register (CANx_CTRL2) This register contains control bits for CAN errors, FIFO features, and mode selection.
PAGE 1133
Chapter 45 CAN (FlexCAN) CANx_CTRL2 field descriptions (continued) Field Description Considering that the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should be programmed with a value correponding to a number of filters not greater than the number of available memory words which can be calculated as follows: (SETUP_MB - 6) × 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
PAGE 1134
Memory map/register definition CANx_CTRL2 field descriptions (continued) Field Description The optimal arbitration timing is that in which the last MB is scanned right before the first bit of the Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial clock ratio is high and the CAN baud rate is low then the arbitration can be delayed and vice-versa.
PAGE 1135
Chapter 45 CAN (FlexCAN) CANx_CTRL2 field descriptions (continued) Field Description This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process. This bit does not affect matching for Rx FIFO. This bit can be written only in Freeze mode because it is blocked by hardware in other modes. 0 1 15–0 Reserved Rx Mailbox filter’s IDE bit is always compared and RTR is never compared despite mask bits.
PAGE 1136
Memory map/register definition CANx_ESR2 field descriptions (continued) Field Description This bit indicates whether IMB and LPTM contents are currently valid or not. VPS is asserted upon every complete Tx arbitration process unless the CPU writes to Control and Status word of a Mailbox that has already been scanned, that is, it is behind Tx Arbitration Pointer, during the Tx arbitration process. If there is no inactive Mailbox and only one Tx Mailbox that is being transmitted then VPS is not asserted.
PAGE 1137
Chapter 45 CAN (FlexCAN) CANx_CRCR field descriptions Field Description 31–23 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 22–16 MBCRC CRC Mailbox This field indicates the number of the Mailbox corresponding to the value in TXCRC field. 15 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 14–0 TXCRC CRC Transmitted This field indicates the CRC value of the last message transmitted.
PAGE 1138
Memory map/register definition CANx_RXFGMASK field descriptions (continued) Field Description Rx FIFO ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter Fields RTR IDE RXIDA A FGM[31] FGM[30] FGM[29:1] B FGM[31], FGM[15] FGM[30], FGM[14] C - - RXIDB1 RXIDC2 - - Reserved FGM[0] FGM[29:16], FGM[13:0] - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0] 1.
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Chapter 45 CAN (FlexCAN) CANx_RXFIR field descriptions Field Description 31–9 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 8–0 IDHIT Identifier Acceptance Filter Hit Indicator This field indicates which Identifier Acceptance Filter was hit by the received message that is in the output of the Rx FIFO. If multiple filters match the incoming message ID then the first matching IDAF found (lowest number) by the matching process is indicated.
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Memory map/register definition CANx_RXIMRn field descriptions (continued) Field Description 0 1 The corresponding bit in the filter is "don't care." The corresponding bit in the filter is checked. 45.3.34 Message buffer structure The Message Buffer structure used by the FlexCAN module is represented in the following figure. Both Extended and Standard Frames, 29-bit Identifier and 11-bit Identifier, respectively, used in the CAN specification (Version 2.0 Part B) are represented.
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Chapter 45 CAN (FlexCAN) Table 45-70. Message buffer code for Rx buffers (continued) CODE Description Rx Code BEFORE receive New Frame SRV1 Rx Code AFTER successful reception2 RRS3 Comment 0b0100: EMPTY MB is active and empty. EMPTY - FULL - When a frame is received successfully (after the Move-in) process), the CODE field is automatically updated to FULL. 0b0010: FULL - MB is full.
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Memory map/register definition Table 45-70. Message buffer code for Rx buffers (continued) CODE Description Rx Code BEFORE receive New Frame SRV1 Rx Code AFTER successful reception2 RRS3 Comment 0b0110: OVERRUN - MB is being overwritten into a full buffer. OVERRUN Yes FULL - If the CODE field indicates OVERRUN and CPU has serviced the MB, when a new frame is moved to the MB, the code returns to FULL.
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Chapter 45 CAN (FlexCAN) Table 45-70. Message buffer code for Rx buffers (continued) CODE Description Rx Code BEFORE receive New Frame SRV1 Rx Code AFTER successful reception2 RRS3 Comment CODE[0]=1b1: BUSY - FlexCAN is updating the contents of the MB. The CPU must not access the MB. BUSY5 - FULL - - OVERRUN - Indicates that the MB is being updated, it will be negated automatically and does not interfere on the next CODE. 1. 2. 3. 4. 5. SRV: Serviced MB.
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Memory map/register definition Table 45-71. Message buffer code for Tx buffers (continued) CODE Description Tx Code BEFORE tx frame MB RTR Tx Code AFTER successful transmission Comment 0b1110: TANSWER MB is a Tx Response Frame from an incoming Remote Request Frame TANSWER - RANSWER This is an intermediate code that is automatically written to the MB by the CHI as a result of match to a remote request frame.
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Chapter 45 CAN (FlexCAN) If FlexCAN transmits this bit as '1' (recessive) and receives it as '0' (dominant), it is interpreted as arbitration loss. If this bit is transmitted as '0' (dominant), then if it is received as '1' (recessive), the FlexCAN module treats it as bit error. If the value received matches the value transmitted, it is considered as a successful bit transmission. 1 = Indicates the current MB may have a Remote Request Frame to be transmitted if MB is Tx.
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Memory map/register definition Table 45-72. DATA BYTEs validity DLC Valid DATA BYTEs 0 none 1 DATA BYTE 0 2 DATA BYTE 0-1 3 DATA BYTE 0-2 4 DATA BYTE 0-3 5 DATA BYTE 0-4 6 DATA BYTE 0-5 7 DATA BYTE 0-6 8 DATA BYTE 0-7 45.3.35 Rx FIFO structure When the MCR[RFEN] bit is set, the memory area from 0x80 to 0xDC (which is normally occupied by MBs 0 to 5) is used by the reception FIFO engine.
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Chapter 45 CAN (FlexCAN) Table 45-73. Rx FIFO structure (continued) 0xE0 ID Filter Table Element 0 0xE4 ID Filter Table Element 1 0xE8 to ID Filter Table Elements 2 to 125 0x2D4 0x2D8 ID Filter Table Element 126 0x2DC ID Filter Table Element 127 = Unimplemented or Reserved Each ID Filter Table Element occupies an entire 32-bit word and can be compound by one, two, or four Identifier Acceptance Filters (IDAF) depending on the MCR[IDAM] field setting. The following figures show the IDAF indexation.
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Functional description 0 = Extended frames are rejected and standard frames can be accepted RXIDA — Rx Frame Identifier (Format A) Specifies an ID to be used as acceptance criteria for the FIFO. In the standard frame format, only the 11 most significant bits (29 to 19 ) are used for frame identification. In the extended frame format, all bits are used. RXIDB_0, RXIDB_1 — Rx Frame Identifier (Format B) Specifies an ID to be used as acceptance criteria for the FIFO.
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Chapter 45 CAN (FlexCAN) 45.4.1 Transmit process To transmit a CAN frame, the CPU must prepare a Message Buffer for transmission by executing the following procedure: 1. Check whether the respective interrupt bit is set and clear it. 2. If the MB is active (transmission pending), write the ABORT code (0b1001) to the CODE field of the Control and Status word to request an abortion of the transmission.
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Functional description 45.4.2 Arbitration process The arbitration process scans the Mailboxes searching the Tx one that holds the message to be sent in the next opportunity. This Mailbox is called the arbitration winner. The scan starts from the lowest number Mailbox and runs toward the higher ones. The arbitration process is triggered in the following events: • From the CRC field of the CAN frame. The start point depends on the CTRL2[TASD] field value. • During the Error Delimiter field of a CAN frame.
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Chapter 45 CAN (FlexCAN) 45.4.2.2 Highest-priority Mailbox first If CTRL1[LBUF] bit is negated, then the arbitration process searches the active Tx Mailbox with the highest priority, which means that this Mailbox’s frame would have a higher probability to win the arbitration on CAN bus when multiple external nodes compete for the bus at the same time. The sequence of bits considered for this arbitration is called the arbitration value of the Mailbox.
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Functional description As the PRIO field is the most significant part of the arbitration value Mailboxes with low PRIO values have higher priority than Mailboxes with high PRIO values regardless the rest of their arbitration values. Note that the PRIO field is not part of the frame on the CAN bus. Its purpose is only to affect the internal arbitration process. 45.4.2.
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Chapter 45 CAN (FlexCAN) Arbitration process stops in the following situation: • • • • All Mailboxes were scanned A Tx active Mailbox is found in case of Lowest Buffer feature enabled Arbitration winner inactivation or abort during any arbitration process There was not enough time to finish Tx arbitration process (for instance, when a deactivation was performed near the end of frame). In this case arbitration process is pending.
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Functional description 1. The received Data field (8 bytes at most) is stored. 2. The received Identifier field is stored. 3. The value of the Free Running Timer at the time of the second bit of frame’s Identifier field is written into the Mailbox’s Time Stamp field. 4. The received SRR, IDE, RTR, and DLC fields are stored. 5. The CODE field in the Control and Status word is updated (see Table 45-70 and Table 45-71 in Section Message buffer structure). 6.
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Chapter 45 CAN (FlexCAN) Note that the received frame’s Identifier field is always stored in the matching Mailbox, thus the contents of the ID field in an Mailbox may change if the match was due to masking. Note also that FlexCAN does receive frames transmitted by itself if there exists a matching Rx Mailbox, provided the MCR[SRXDIS] bit is not asserted.
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Functional description • If the received frame is a data frame with DLC field equal to zero, the start point is the CRC field of the frame • If the received frame is a data frame with DLC field different than zero, the start point is the DATA field of the frame If a matching ID is found in the FIFO table or in one of the Mailboxes, the contents of the SMB will be transferred to the FIFO or to the matched Mailbox by the move-in process.
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Chapter 45 CAN (FlexCAN) • The CODE field of the Mailbox is either FULL or OVERRUN and it has already been serviced (the C/S word was read by the CPU and unlocked as described in Mailbox lock mechanism) • The CODE field of the Mailbox is either FULL or OVERRUN and an inactivation (see Mailbox inactivation) is performed • The Rx FIFO is not full The scan order for Mailboxes and Rx FIFO is from the matching element with lowest number to the higher ones.
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Functional description Table 45-78.
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Chapter 45 CAN (FlexCAN) 3. This is a forbidden condition. 4. Matched in MB “Free” means that the frame matched at least one MB free-to-receive regardless of whether it has matched MBs non-free-to-receive. 5. Matched in FIFO “None” means that the frame has not matched any filter in FIFO. It is as if the FIFO didn’t exist (CTRL2[RFEN]=0). 6. Matched in FIFO “NotFull” means that the frame has matched a FIFO filter and has empty slots to receive it. 7.
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Functional description 45.4.5 Move process There are two types of move process: move-in and move-out. 45.4.5.1 Move-in The move-in process is the copy of a message received by an Rx SMB to a Rx Mailbox or FIFO that has matched it. If the move destination is the Rx FIFO, attributes of the message are also copied to the RXFIR FIFO. Each Rx SMB has its own move-in process, but only one is performed at a given time as described ahead.
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Chapter 45 CAN (FlexCAN) The move-in process is the execution by the FlexCAN of the following steps: 1. 2. 3. 4. 5. if the message is destined to the Rx FIFO, push IDHIT into the RXFIR FIFO; reads the words DATA0-3 and DATA4-7 from the Rx SMB; writes it in the words DATA0-3 and DATA4-7 of the Rx Mailbox; reads the words Control/Status and ID from the Rx SMB; writes it in the words Control/Status and ID of the Rx Mailbox, updating the CODE field.
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Functional description 45.4.6.1 Transmission abort mechanism The abort mechanism provides a safe way to request the abortion of a pending transmission. A feedback mechanism is provided to inform the CPU if the transmission was aborted or if the frame could not be aborted and was transmitted instead.
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Chapter 45 CAN (FlexCAN) • CPU writes 0b1001 into the CODE field of the C/S word. • CPU waits for the corresponding IFLAG indicating that the frame was either transmitted or aborted. • CPU reads the CODE field to check if the frame was either transmitted (CODE=0b1000) or aborted (CODE=0b1001). • It is necessary to clear the corresponding IFLAG in order to allow the MB to be reconfigured. 45.4.6.
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Functional description FlexCAN. CPU must maintain data coherency in the FIFO region when RFEN is asserted. 45.4.6.3 Mailbox lock mechanism Other than Mailbox inactivation, FlexCAN has another data coherence mechanism for the receive process. When the CPU reads the Control and Status word of an Rx MB with codes FULL or OVERRUN, FlexCAN assumes that the CPU wants to read the whole MB in an atomic operation, and therefore it sets an internal lock flag for that MB.
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Chapter 45 CAN (FlexCAN) Note If the BUSY bit is asserted or if the MB is empty, then reading the Control and Status word does not lock the MB. Inactivation takes precedence over locking. If the CPU inactivates a locked Rx MB, then its lock status is negated and the MB is marked as invalid for the current matching round. Any pending message on the SMB will not be transferred anymore to the MB.
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Functional description The IFLAG[BUF7I] (Rx FIFO Overflow) is asserted when an incoming message was lost because the Rx FIFO is full. Note that the flag will not be asserted when the Rx FIFO is full and the message was captured by a Mailbox. The flag remains asserted until the CPU clears it. Clearing one of those three flags does not affect the state of the other two. An interrupt is generated if an IFLAG bit is asserted and the corresponding mask bit is asserted too.
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Chapter 45 CAN (FlexCAN) 45.4.8.1 Remote frames Remote frame is a special kind of frame. The user can program a mailbox to be a Remote Request Frame by writing the mailbox as Transmit with the RTR bit set to '1'. After the remote request frame is transmitted successfully, the mailbox becomes a Receive Message Buffer, with the same ID as before.
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Functional description • Detection of a dominant bit in the first/second bit of Intermission • Detection of a dominant bit at the 7th bit (last) of End of Frame field (Rx frames) • Detection of a dominant bit at the 8th bit (last) of Error Frame Delimiter or Overload Frame Delimiter 45.4.8.
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Chapter 45 CAN (FlexCAN) The PRESDIV field controls a prescaler that generates the Serial Clock (Sclock), whose period defines the 'time quantum' used to compose the CAN waveform. A time quantum is the atomic unit of time handled by the CAN engine. f CANCLK f Tq = (Prescaler Value) A bit time is subdivided into three segments2 (see Figure 45-67 and Table 45-79): • SYNC_SEG: This segment has a fixed length of one time quantum.
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Functional description Whenever CAN bit is used as a measure of duration (e.g.
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Chapter 45 CAN (FlexCAN) Note The user must ensure the bit time settings are in compliance with the CAN standard. For bit time calculations, use an IPT (Information Processing Time) of 2, which is the value implemented in the FlexCAN module. 45.4.8.5 Arbitration and matching timing During normal reception and transmission of frames, the matching, arbitration, move-in and move-out processes are executed during certain time windows inside the CAN frame, as shown in the following figures.
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Functional description concurrent memory access due to the CPU or other internal FlexCAN sub-blocks. When doing matching and arbitration, FlexCAN needs to scan the whole Message Buffer memory during the available time slot.
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Chapter 45 CAN (FlexCAN) As an example, taking the case of 64 MBs, if the oscillator and peripheral clock frequencies are equal and the CAN bit timing is programmed to have 8 time quanta per bit, then the prescaler factor (PRESDIV + 1) should be at least 2. For prescaler factor equal to one and CAN bit timing with 8 time quanta per bit, the ratio between peripheral and oscillator clock frequencies should be at least 2. 45.4.
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Functional description 45.4.10.1 Freeze mode This mode is requested by the CPU through the assertion of the HALT bit in the MCR Register or when the MCU is put into Debug mode. In both cases it is also necessary that the FRZ bit is asserted in the MCR Register and the module is not in a low-power mode. The acknowledgement is obtained through the assertion by the FlexCAN of FRZ_ACK bit in the same register.
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Chapter 45 CAN (FlexCAN) 45.4.10.2 Module Disable mode This low power mode is normally used to temporarily disable a complete FlexCAN block, with no power consumption. It is requested by the CPU through the assertion of the MDIS bit in the MCR Register and the acknowledgement is obtained through the assertion by the FlexCAN of the LPM_ACK bit in the same register. The CPU must only consider the FlexCAN in Disable mode when both request and acknowledgement conditions are satisfied.
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Functional description If FlexCAN receives the global Stop mode request during Freeze mode, it sets the LPMACK bit, negates the FRZACK bit and then sends the Stop Acknowledge signal to the CPU, in order to shut down the clocks globally.
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Chapter 45 CAN (FlexCAN) 45.4.11 Interrupts The module has many interrupt sources: interrupts due to message buffers and interrupts due to the ORed interrupts from MBs, Bus Off, Error, Wake Up, Tx Warning, and Rx Warning. Each one of the message buffers can be an interrupt source, if its corresponding IMASK bit is set. There is no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the buffer is initialized for either transmission or reception.
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Initialization/application information • Unrestricted read and write access to supervisor registers (registers identified with S/ U in Table "Module Memory Map" in Supervisor Mode or with S only) results in access error. • Read and write access to implemented reserved address space results in access error. • Write access to positions whose bits are all currently read-only results in access error. If at least one of the bits is not read-only then no access error is issued.
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Chapter 45 CAN (FlexCAN) • MCU level soft reset, which resets some of the memory mapped registers synchronously. See Table 45-2 to see what registers are affected by soft reset. • SOFT_RST bit in MCR, which has the same effect as the MCU level soft reset Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. Therefore, it may take some time to fully propagate its effects.
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Initialization/application information • Determine the bit rate by programming the PRESDIV field • Determine the internal arbitration mode (LBUF bit) • Initialize the Message Buffers • The Control and Status word of all Message Buffers must be initialized • If Rx FIFO was enabled, the ID filter table must be initialized • Other entries in each Message Buffer should be initialized as required • Initialize the Rx Individual Mask Registers • Set required interrupt mask bits in the IMASK Registers (for all MB
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Chapter 46 Serial Peripheral Interface (SPI) 46.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The serial peripheral interface (SPI) module provides a synchronous serial bus for communication between an MCU and an external peripheral device. 46.1.1 Block Diagram The block diagram of this module is as follows: K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 Freescale Semiconductor, Inc.
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Introduction INTC eDMA Slave Bus Interface Clock/Reset SPI DMA and Interrupt Control POPR TX FIFO RX FIFO PUSHR CMD Data Data 32 32 SOUT Shift Register SIN SCK S PI Baud Rate, Delay & Transfer Control PCS[x]/SS 8 Figure 46-1. SPI Block Diagram 46.1.
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Chapter 46 Serial Peripheral Interface (SPI) • Visibility into TX and RX FIFOs for ease of debugging • Programmable transfer attributes on a per-frame basis: • two transfer attribute registers • Serial clock (SCK) with programmable polarity and phase • Various programmable delays • Programmable serial frame size of 4–16 bits, expandable by software control • SPI frames longer than 16 bits can be supported using the continuous selection format • Continuously held chip select capability • 5 peripheral chip s
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Introduction 46.1.3 Module Configurations The module supports SPI configuration. 46.1.3.1 SPI Configuration The SPI configuration allows the module to send and receive serial data. This configuration allows the module to operate as a basic SPI block with internal FIFOs supporting external queue operation. Transmitted data and received data reside in separate FIFOs. The host CPU or a DMA controller read the received data from the Receive FIFO and write transmit data to the Transmit FIFO.
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Chapter 46 Serial Peripheral Interface (SPI) • Slave mode • Module Disable mode • MCU-specific modes: • External Stop mode • Debug mode The module enters module-specific modes when the host writes a module register. The MCU-specific modes are controlled by signals external to the module. The MCU-specific modes are modes that an MCU may enter in parallel to the block-specific modes. 46.1.4.1 Master Mode Master mode allows the module to initiate and control serial communication.
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Module signal descriptions 46.1.4.5 Debug Mode Debug mode is used for system development and debugging. The MCR[FRZ] bit controls module behavior in the Debug mode: • If the bit is set, the module stops all serial transfers, when the MCU is in debug mode. • If the bit is cleared, the MCU debug mode has no effect on the module. 46.2 Module signal descriptions This section provides description of the module signals.
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Chapter 46 Serial Peripheral Interface (SPI) 46.2.3 PCS4 — Peripheral Chip Select 4 In Master mode, PCS4 is an output signal. In Slave mode, this signal is unused. 46.2.4 SIN — Serial Input SIN is a serial data input signal. 46.2.5 SOUT — Serial Output SOUT is a serial data output signal. 46.2.6 SCK — Serial Clock SCK is a serial communication clock signal. In Master mode, the module generates the SCK. In Slave mode, SCK is an input from an external bus master. 46.
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Memory Map/Register Definition SPI memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_C030 DSPI DMA/Interrupt Request Select and Enable Register (SPI0_RSER) 32 R/W 0000_0000h 46.3.6/1203 4002_C034 DSPI PUSH TX FIFO Register In Master Mode (SPI0_PUSHR) 32 R/W 0000_0000h 46.3.7/1205 4002_C034 DSPI PUSH TX FIFO Register In Slave Mode (SPI0_PUSHR_SLAVE) 32 R/W 0000_0000h 46.3.
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Chapter 46 Serial Peripheral Interface (SPI) SPI memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_D044 DSPI Transmit FIFO Registers (SPI1_TXFR2) 32 R 0000_0000h 46.3.10/ 1208 4002_D048 DSPI Transmit FIFO Registers (SPI1_TXFR3) 32 R 0000_0000h 46.3.10/ 1208 4002_D07C DSPI Receive FIFO Registers (SPI1_RXFR0) 32 R 0000_0000h 46.3.11/ 1208 4002_D080 DSPI Receive FIFO Registers (SPI1_RXFR1) 32 R 0000_0000h 46.3.
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Memory Map/Register Definition 46.3.1 Module Configuration Register (SPIx_MCR) Contains bits to configure various attributes associated with the module operations. The HALT and MDIS bits can be changed at any time, but the effect takes place only on the next frame boundary. Only the HALT and MDIS bits in the MCR can be changed, while the module is in the Running state.
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Chapter 46 Serial Peripheral Interface (SPI) SPIx_MCR field descriptions Field 31 MSTR Description Master/Slave Mode Select Configures the DSPI for either Master mode or Slave mode. 0 1 30 CONT_SCKE Continuous SCK Enable Enables the Serial Communication Clock (SCK) to run continuously. 0 1 29–28 DCONF Selects among the different configurations of the DSPI. Enables the DSPI transfers to be stopped on the next frame boundary when the device enters Debug mode.
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Memory Map/Register Definition SPIx_MCR field descriptions (continued) Field 15 DOZE Description Doze Enable Provides support for an externally controlled Doze mode power-saving mechanism. 0 1 14 MDIS Module Disable Allows the clock to be stopped to the non-memory mapped logic in the module effectively putting it in a software-controlled power-saving state. The reset value of the MDIS bit is parameterized, with a default reset value of 0.
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Chapter 46 Serial Peripheral Interface (SPI) SPIx_MCR field descriptions (continued) Field Description 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 HALT Halt Starts and stops the module transfers. 0 1 Start transfers. Stop transfers. 46.3.2 DSPI Transfer Count Register (SPIx_TCR) TCR contains a counter that indicates the number of SPI transfers made.
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Memory Map/Register Definition In Master mode, the CTARs define combinations of transfer attributes such as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. In Slave mode, a subset of the fields in CTAR0 are used to set the slave transfer attributes. When the DSPI is configured as an SPI master, the CTAS field in the command portion of the TX FIFO entry selects which of the CTAR register is used. When the DSPI is configured as an SPI bus slave, the CTAR0 is used.
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Chapter 46 Serial Peripheral Interface (SPI) SPIx_CTARn field descriptions (continued) Field Description 0 1 The baud rate is computed normally with a 50/50 duty cycle. The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. 30–27 FMSZ Frame Size 26 CPOL Clock Polarity The number of bits transferred per frame is equal to the FMSZ field value plus 1. The minimum valid FMSZ field value is 3. Selects the inactive state of the SCK.
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Memory Map/Register Definition SPIx_CTARn field descriptions (continued) Field 19–18 PDT Description Delay after Transfer Prescaler Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next frame. The PDT field is used only in Master mode. See the DT field description for details on how to compute the Delay after Transfer. See Delay after Transfer (tDT) for more details.
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Chapter 46 Serial Peripheral Interface (SPI) SPIx_CTARn field descriptions (continued) Field Description Table 46-39. Delay scaler encoding (continued) Field value Delay scaler value 1110 32768 1111 65536 See PCS to SCK Delay (tCSC) for more details. 11–8 ASC After SCK Delay Scaler Selects the scaler value for the After SCK Delay. This field is used only in Master mode. The After SCK Delay is the delay between the last edge of SCK and the negation of PCS.
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Memory Map/Register Definition SPIx_CTARn field descriptions (continued) Field Description Table 46-40. DSPI baud rate scaler (continued) CTARn[BR] Baud rate scaler value 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768 46.3.4 DSPI Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE) When the DSPI is configured as an SPI bus slave, the CTAR0 register is used.
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Chapter 46 Serial Peripheral Interface (SPI) SPIx_CTARn_SLAVE field descriptions (continued) Field Description Selects the inactive state of the Serial Communications Clock (SCK). 0 1 25 CPHA The inactive state value of SCK is low. The inactive state value of SCK is high. Clock Phase Selects which edge of SCK causes data to change and which edge causes data to be captured. This bit is used in both master and slave mode.
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Memory Map/Register Definition 46.3.5 DSPI Status Register (SPIx_SR) SR contains status and flag bits. The bits reflect the status of the DSPI and indicate the occurrence of events that can generate interrupt or DMA requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0 to a flag bit has no effect. This register may not be writable in Module Disable mode due to the use of power saving mechanisms.
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Chapter 46 Serial Peripheral Interface (SPI) SPIx_SR field descriptions (continued) Field 28 EOQF Description End of Queue Flag Indicates that the last entry in a queue has been transmitted when the DSPI is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit set in the command halfword and the end of the transfer is reached. The EOQF bit remains set until cleared by writing a 1 to it. When the EOQF bit is set, the TXRXS bit is automatically cleared.
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Memory Map/Register Definition SPIx_SR field descriptions (continued) Field Description Provides a method for the DSPI to request that entries be removed from the RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be cleared by writing 1 to it or by acknowledgement from the DMA controller when the RX FIFO is empty. 0 1 16 Reserved 15–12 TXCTR 11–8 TXNXTPTR RX FIFO is empty. RX FIFO is not empty. This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 46 Serial Peripheral Interface (SPI) 46.3.6 DSPI DMA/Interrupt Request Select and Enable Register (SPIx_RSER) RSER controls DMA and interrupt requests. Do not write to the RSER while the DSPI is in the Running state.
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Memory Map/Register Definition SPIx_RSER field descriptions (continued) Field Description 26 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 25 TFFF_RE Transmit FIFO Fill Request Enable Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit selects between generating an interrupt request or a DMA request. 0 1 24 TFFF_DIRS TFFF interrupts or DMA requests are disabled. TFFF interrupts or DMA requests are enabled.
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Chapter 46 Serial Peripheral Interface (SPI) SPIx_RSER field descriptions (continued) Field Description 14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 46.3.7 DSPI PUSH TX FIFO Register In Master Mode (SPIx_PUSHR) PUSHR provides the means to write to the TX FIFO. Data written to this register is transferred to the TX FIFO .
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Memory Map/Register Definition SPIx_PUSHR field descriptions (continued) Field Description 0 1 30–28 CTAS Clock and Transfer Attributes Select Selects which CTAR to use in master mode to specify the transfer attributes for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chapter on chip configuration to determine how many CTARs this device has. You should not program a value in this field for a register that is not present.
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Chapter 46 Serial Peripheral Interface (SPI) 46.3.8 DSPI PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE) PUSHR provides the means to write to the TX FIFO. Data written to this register is transferred to the TX FIFO. Eight- or sixteen-bit write accesses to the Data Field of PUSHR transfers the 16 bit Data Field of PUSHR to the TX FIFO. The register structure is different in master and slave modes. The register structure is different in master and slave modes.
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Memory Map/Register Definition SPIx_POPR field descriptions Field Description 31–0 RXDATA Received Data Contains the SPI data from the RX FIFO entry to which the Pop Next Data Pointer points. 46.3.10 DSPI Transmit FIFO Registers (SPIx_TXFRn) TXFRn registers provide visibility into the TX FIFO for debugging purposes. Each register is an entry in the TX FIFO. The registers are read-only and cannot be modified. Reading the TXFRx registers does not alter the state of the TX FIFO.
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Chapter 46 Serial Peripheral Interface (SPI) SPIx_RXFRn field descriptions Field 31–0 RXDATA Description Receive Data Contains the received SPI data. 46.4 Functional description The Serial Peripheral Interface (DSPI) block supports full-duplex, synchronous serial communications between MCUs and peripheral devices. The SPI configuration transfers data serially using a shift register and a selection of programmable transfer attributes.
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Functional description Generally, more than one slave device can be connected to the module master. Six Peripheral Chip Select (PCS) signals of the module masters can be used to select which of the slaves to communicate with. Refer to the chip configuration chapter for the number of PCS signals used in this MCU. The SPI configuration share transfer protocol and timing properties which are described independently of the configuration in Transfer formats .
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Chapter 46 Serial Peripheral Interface (SPI) 46.4.2 Serial Peripheral Interface (SPI) configuration The SPI configuration transfers data serially using a shift register and a selection of programmable transfer attributes. The module is in SPI configuration when the DCONF field in the MCR is 0b00. The SPI frames can be 32 bits long. The host CPU or a DMA controller transfers the SPI data from the external to DSPI RAM queues to a TX FIFO buffer. The received data is stored in entries in the RX FIFO buffer.
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Functional description 46.4.2.3 FIFO disable operation The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX FIFO. The module operates as a double-buffered simplified SPI when the FIFOs are disabled. The Transmit and Receive side of the FIFOs are disabled separately; setting the MCR[DIS_TXF] bit disables the TX FIFO, and setting the MCR[DIS_RXF] bit disables the RX FIFO. The FIFO disable mechanisms are transparent to the user and to host software.
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Chapter 46 Serial Peripheral Interface (SPI) The module ignores attempts to push data to a full TX FIFO, and the state of the TX FIFO does not change and no error condition is indicated. 46.4.2.4.2 Draining the TX FIFO The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the TX FIFO.
PAGE 1214
Functional description 46.4.2.5.1 Filling the RX FIFO The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full, SPI frames from the shift register are transferred to the RX FIFO. Every time an SPI frame is transferred to the RX FIFO, the RX FIFO Counter is incremented by one. If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the SR is set indicating an overflow condition.
PAGE 1215
Chapter 46 Serial Peripheral Interface (SPI) Table 46-98. Baud rate computation example fSYS PBR Prescaler BR Scaler DBR Baud rate 100 MHz 0b00 2 0b0000 2 0 25 Mb/s 20 MHz 0b00 2 0b0000 2 1 10 Mb/s NOTE The clock frequencies mentioned in the preceding table are given as an example. Refer to the clocking chapter for the frequency used to drive this module in the device. 46.4.3.
PAGE 1216
Functional description NOTE The clock frequency mentioned in the preceding table is given as an example. Refer to the clocking chapter for the frequency used to drive this module in the device. 46.4.3.4 Delay after Transfer (tDT) The Delay after Transfer is the minimum time between negation of the PCS signal for a frame and the assertion of the PCS signal for the next frame. See Figure 46-71 for an illustration of the Delay after Transfer.
PAGE 1217
Chapter 46 Serial Peripheral Interface (SPI) Even though the bus slave does not control the SCK signal, in Slave mode these values must be identical to the master device settings to ensure proper transmission. In SPI Slave mode, only CTAR0 is used.
PAGE 1218
Functional description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK (CPOL = 0) SCK (CPOL = 1) Master and Slave Sample Master SOUT/ Slave SIN Master SIN/ Slave SOUT PCSx/SS tASC tDT t CSC tCSC Bit 6 Bit 5 Bit 4 MSB first (LSBFE = 0): MSB Bit 1 Bit 2 Bit 3 MSB first (LSBFE = 1): LSB tCSC = PCS to SCK delay tASC = After SCK delay tDT = Delay after Transfer (Minimum CS idle time) Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 46-71.
PAGE 1219
Chapter 46 Serial Peripheral Interface (SPI) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK (CPOL = 0) SCK (CPOL = 1) Master and Slave Sample Master SOUT/ Slave SIN Master SIN/ Slave SOUT PCSx/SS tASC tDT tCSC Bit 4 Bit 5 Bit 3 MSB first (LSBFE = 0): MSB Bit 6 Bit 1 Bit 2 LSB first (LSBFE = 1): LSB Bit 4 Bit 3 P tCSC = CS to SCK delay tASC = After SCK delay tDT = Delay after Transfer (minimum CS negation time) Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 46-72.
PAGE 1220
Functional description When the CONT bit = 0, the module drives the asserted Chip Select signals to their idle states in between frames. The idle states of the Chip Select signals are selected by the PCSISn bits in the MCR. The following timing diagram is for two four-bit transfers with CPHA = 1 and CONT = 0. SCK (CPOL = 0) SCK (CPOL = 1) Master SOUT Master SIN PCSx tCSC t ASC t DT t CSC tCSC = PCS to SCK dela t ASC = After SCK delay t DT = Delay after Transfer (minimum CS negation time) Figure 46-73.
PAGE 1221
Chapter 46 Serial Peripheral Interface (SPI) • All transmit commands must have the same PCSn bits programming. • The CTARs, selected by transmit commands, must be programmed with the same transfer attributes. Only FMSZ field can be programmed differently in these CTARs.
PAGE 1222
Functional description • When the module is in SPI configuration, CTAR0 is used initially. At the start of each SPI frame transfer, the CTAR specified by the CTAS for the frame is used. • In all configurations, the currently selected CTAR remains in use until the start of a frame with a different CTAR specified, or the Continuous SCK mode is terminated. It is recommended to keep the baud rate the same while using the Continuous SCK.
PAGE 1223
Chapter 46 Serial Peripheral Interface (SPI) • Continuous SCK with CONT bit set and entering Stopped state (refer to Start and Stop of module transfers). • Continuous SCK with CONT bit set and entering Stop mode or Module Disable mode. The following figure shows timing diagram for Continuous SCK format with Continuous Selection enabled. SCK (CPOL = 0) SCK (CPOL = 1) Master SOUT Master SIN PCS transfer 1 transfer 2 Figure 46-76. Continuous SCK timing diagram (CONT=1) 46.4.
PAGE 1224
Functional description Table 46-102. Interrupt and DMA request conditions Condition Flag Interrupt DMA End of Queue (EOQ) EOQF Yes - TX FIFO Fill TFFF Yes Yes Transfer Complete TCF Yes - TX FIFO Underflow TFUF Yes - RX FIFO Drain RFDF Yes Yes RX FIFO Overflow RFOF Yes - Each condition has a flag bit in the module Status Register (SR) and a Request Enable bit in the DMA/Interrupt Request Select and Enable Register (RSER).
PAGE 1225
Chapter 46 Serial Peripheral Interface (SPI) To clear TFFF when not using DMA, follow these steps for every PUSH performed using CPU to fill TX FIFO: 1. Wait until TFFF = 1. 2. Write data to PUSHR using CPU. 3. Clear TFFF by writing a 1 to its location. If TX FIFO is not full, this flag will not clear. 46.4.7.3 Transfer Complete Interrupt Request The Transfer Complete Request indicates the end of the transfer of a serial frame.
PAGE 1226
Functional description Depending on the state of the ROOE bit in the MCR, the data from the transfer that generated the overflow is either ignored or shifted in to the shift register. If the ROOE bit is set, the incoming data is shifted in to the shift register. If the ROOE bit is cleared, the incoming data is ignored. 46.4.8 Power saving features The module supports following power-saving strategies: • External Stop mode • Module Disable mode – Clock gating of non-memory mapped logic 46.4.8.
PAGE 1227
Chapter 46 Serial Peripheral Interface (SPI) Register does not change the state of the TX FIFO. Clearing either of the FIFOs has no effect in the Module Disable mode. Changes to the DIS_TXF and DIS_RXF fields of the MCR have no effect in the Module Disable mode. In the Module Disable mode, all status bits and register flags in the module return the correct values when read, but writing to them has no effect. Writing to the TCR during Module Disable mode has no effect.
PAGE 1228
Initialization/application information 10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the module TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit. 11. Enable serial transmission and serial reception of data by clearing the EOQF bit. 46.5.2 Switching Master and Slave mode When changing modes in the module, follow the steps below to guarantee proper operation. 1. Halt it by setting MCR[HALT]. 2.
PAGE 1229
Chapter 46 Serial Peripheral Interface (SPI) Table 46-103. Baud rate values (bps) Baud Rate Scaler Values Baud rate divider prescaler values 2 3 5 7 2 25.0M 16.7M 10.0M 7.14M 4 12.5M 8.33M 5.00M 3.57M 6 8.33M 5.56M 3.33M 2.38M 8 6.25M 4.17M 2.50M 1.79M 16 3.12M 2.08M 1.25M 893k 32 1.56M 1.04M 625k 446k 64 781k 521k 312k 223k 128 391k 260k 156k 112k 256 195k 130k 78.1k 55.8k 512 97.7k 65.1k 39.1k 27.9k 1024 48.8k 32.6k 19.5k 14.0k 2048 24.4k 16.
PAGE 1230
Initialization/application information Table 46-104. Delay values Delay scaler values Delay prescaler values 1 3 5 7 2 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 160.0 ns 480.0 ns 800.0 ns 1.1 μs 32 320.0 ns 960.0 ns 1.6 μs 2.2 μs 64 640.0 ns 1.9 μs 3.2 μs 4.5 μs 128 1.3 μs 3.8 μs 6.4 μs 9.0 μs 256 2.6 μs 7.7 μs 12.8 μs 17.9 μs 512 5.1 μs 15.4 μs 25.6 μs 35.8 μs 1024 10.2 μs 30.7 μs 51.
PAGE 1231
Chapter 46 Serial Peripheral Interface (SPI) Push TX FIFO Register TX FIFO Base Transmit Next Data Pointer Entry A (first in) Entry B Entry C Entry D (last in) - Shift Register +1 TX FIFO Counter SOUT -1 Figure 46-77. TX FIFO pointers and counter 46.5.6.
PAGE 1232
Initialization/application information The memory address of the last-in entry in the RX FIFO is computed by the following equation: RX FIFO Base - Base address of RX FIFO RXCTR - RX FIFO counter POPNXTPTR - Pop Next Pointer RX FIFO Depth - Receive FIFO depth, implementation specific K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 1232 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 1233
Chapter 47 Inter-Integrated Circuit (I2C) 47.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The inter-integrated circuit (I2C, I2C, or IIC) module provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbit/s with maximum bus loading and timing. The I2C device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading.
PAGE 1234
Introduction • • • • • • 10-bit address extension Support for System Management Bus (SMBus) Specification, version 2 Programmable glitch input filter Low power mode wakeup on slave address match Range slave address support DMA support 47.1.2 Modes of operation The I2C module's operation in various low power modes is as follows: • Run mode: This is the basic mode of operation. To conserve power in this mode, disable the module.
PAGE 1235
Chapter 47 Inter-Integrated Circuit (I2C) Address Module Enable Write/Read Interrupt ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync START STOP Arbitration Control Clock Control In/Out Data Shift Register Address Compare SDA SCL Figure 47-1. I2C Functional block diagram 47.2 I2C signal descriptions The signal properties of I2C are shown in the following table. Table 47-1.
PAGE 1236
Memory map and register descriptions I2C memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_6000 I2C Address Register 1 (I2C0_A1) 8 R/W 00h 47.3.1/1236 4006_6001 I2C Frequency Divider register (I2C0_F) 8 R/W 00h 47.3.2/1237 4006_6002 I2C Control Register 1 (I2C0_C1) 8 R/W 00h 47.3.3/1238 4006_6003 I2C Status register (I2C0_S) 8 R/W 80h 47.3.4/1240 4006_6004 I2C Data I/O register (I2C0_D) 8 R/W 00h 47.3.
PAGE 1237
Chapter 47 Inter-Integrated Circuit (I2C) I2Cx_A1 field descriptions Field 7–1 AD[7:1] 0 Reserved Description Address Contains the primary slave address used by the I2C module when it is addressed as a slave. This field is used in the 7-bit address scheme and the lower seven bits in the 10-bit address scheme. This field is reserved. This read-only field is reserved and always has the value 0. 47.3.
PAGE 1238
Memory map and register descriptions I2Cx_F field descriptions (continued) Field Description MULT ICR 2h Hold times (μs) SDA SCL Start SCL Stop 00h 3.500 3.000 5.500 1h 07h 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h 1.125 4.750 5.125 47.3.
PAGE 1239
Chapter 47 Inter-Integrated Circuit (I2C) I2Cx_C1 field descriptions (continued) Field Description Selects the direction of master and slave transfers. In master mode this bit must be set according to the type of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slave this bit must be set by software according to the SRW bit in the status register.
PAGE 1240
Memory map and register descriptions 47.3.4 I2C Status register (I2Cx_S) Address: Base address + 3h offset Bit Read 7 6 TCF IAAS Write Reset 1 5 4 BUSY ARBL 3 RAM w1c 0 0 0 0 2 1 0 SRW IICIF RXAK w1c 0 0 0 I2Cx_S field descriptions Field 7 TCF Description Transfer Complete Flag This bit sets on the completion of a byte and acknowledge bit transfer. This bit is valid only during or immediately following a transfer to or from the I2C module.
PAGE 1241
Chapter 47 Inter-Integrated Circuit (I2C) I2Cx_S field descriptions (continued) Field Description • Any nonzero calling address is received that matches the address in the RA register. • The RMEN bit is set and the calling address is within the range of values of the A1 and RA registers. Writing the C1 register with any value clears this bit. 0 1 2 SRW Slave Read/Write When addressed as a slave, SRW indicates the value of the R/W command bit of the calling address sent to the master.
PAGE 1242
Memory map and register descriptions I2Cx_D field descriptions (continued) Field Description NOTE: When making the transition out of master receive mode, switch the I2C mode before reading the Data register to prevent an inadvertent initiation of a master receive data transfer. In slave mode, the same functions are available after an address match occurs. The C1[TX] bit must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin.
PAGE 1243
Chapter 47 Inter-Integrated Circuit (I2C) I2Cx_C2 field descriptions (continued) Field Description 0 1 3 RMEN Range Address Matching Enable This bit controls slave address matching for addresses between the values of the A1 and RA registers. When this bit is set, a slave address match occurs for any address greater than the value of the A1 register and less than or equal to the value of the RA register.
PAGE 1244
Memory map and register descriptions 47.3.8 I2C Range Address register (I2Cx_RA) Address: Base address + 7h offset Bit Read Write Reset 7 6 5 4 3 2 1 RAD 0 0 0 0 0 0 0 0 0 0 I2Cx_RA field descriptions Field 7–1 RAD 0 Reserved Description Range Slave Address This field contains the slave address to be used by the I2C module. The field is used in the 7-bit address scheme. Any nonzero write enables this register.
PAGE 1245
Chapter 47 Inter-Integrated Circuit (I2C) I2Cx_SMB field descriptions Field 7 FACK Description Fast NACK/ACK Enable For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the result of receiving data byte. 0 1 6 ALERTEN An ACK or NACK is sent on the following receiving data byte Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
PAGE 1246
Memory map and register descriptions I2Cx_SMB field descriptions (continued) Field 0 SHTF2IE Description SHTF2 Interrupt Enable Enables SCL high and SDA low timeout interrupt. 0 1 SHTF2 interrupt is disabled SHTF2 interrupt is enabled 47.3.
PAGE 1247
Chapter 47 Inter-Integrated Circuit (I2C) 47.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL) Address: Base address + Bh offset Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 SSLT[7:0] 0 0 0 0 I2Cx_SLTL field descriptions Field 7–0 SSLT[7:0] Description Least significant byte of SCL low timeout value that determines the timeout period of SCL low. 47.4 Functional description This section provides a comprehensive functional description of the I2C module. 47.4.
PAGE 1248
Functional description M SB SCL SDA 1 SDA Start Signal 3 4 5 6 7 8 9 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W C a llin g A d d re s s Start Signal SCL M SB LSB 2 3 4 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 D a ta B y te 5 6 7 8 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W C a llin g A d d re s s 1 9 R e a d / Ack W rite Bit XX 9 No Stop Ack Signal Bit M SB LSB 2 2 R e a d / Ack W rite Bit M SB 1 XXX LSB 1 LSB 2 3 4 5 6 7 8 9 A D 7 A D 6 A D 5
PAGE 1249
Chapter 47 Inter-Integrated Circuit (I2C) No two slaves in the system can have the same address. If the I2C module is the master, it must not transmit an address that is equal to its own slave address. The I2C module cannot be master and slave at the same time. However, if arbitration is lost during an address cycle, the I2C module reverts to slave mode and operates correctly even if it is being addressed by another master. 47.4.1.
PAGE 1250
Functional description 47.4.1.5 Repeated START signal The master may generate a START signal followed by a calling command without generating a STOP signal first. This action is called a repeated START. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 47.4.1.6 Arbitration procedure The I2C bus is a true multimaster bus that allows more than one master to be connected on it.
PAGE 1251
Chapter 47 Inter-Integrated Circuit (I2C) S ta rt C o u n tin g H ig h P e rio d D e la y SCL1 SCL2 SCL In te rn a l C o u n te r R e s e t Figure 47-39. I2C clock synchronization 47.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfers. A slave device may hold SCL low after completing a single byte transfer (9 bits). In this case, it halts the bus clock and forces the master clock into wait states until the slave releases SCL. 47.4.1.
PAGE 1252
Functional description Table 47-41.
PAGE 1253
Chapter 47 Inter-Integrated Circuit (I2C) 47.4.2.1 Master-transmitter addresses a slave-receiver The transfer direction is not changed. When a 10-bit address follows a START condition, each slave compares the first 7 bits of the first byte of the slave address (11110XX) with its own address and tests whether the eighth bit (R/W direction bit) is 0. It is possible that more than one device finds a match and generates an acknowledge (A1).
PAGE 1254
Functional description Table 47-43. Master-receiver addresses a slave-transmitter with a 10-bit address S Slave address first 7 bits 11110 + AD10 + AD9 R/W 0 A1 Slave address second byte AD[8:1] A2 Sr Slave address first 7 bits 11110 + AD10 + AD9 R/W 1 A3 Data A ... Data A P After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an I2C interrupt.
PAGE 1255
Chapter 47 Inter-Integrated Circuit (I2C) 47.4.4 System management bus specification SMBus provides a control bus for system and power management related tasks. A system can use SMBus to pass messages to and from devices instead of tripping individual control lines. Removing the individual control lines reduces pin count. Accepting messages ensures future expandability.
PAGE 1256
Functional description A HIGH timeout occurs after a START condition appears on the bus but before a STOP condition appears on the bus. Any master detecting this scenario can assume the bus is free when either of the following occurs: • SHTF1 rises. • The BUSY bit is high and SHTF1 is high. When the SMBDAT signal is low and the SMBCLK signal is high for a period of time, another kind of timeout occurs. The time period must be defined in software. SHTF2 is used as the flag when the time limit is reached.
PAGE 1257
Chapter 47 Inter-Integrated Circuit (I2C) 47.4.4.2 FAST ACK and NACK To improve reliability and communication robustness, implementation of packet error checking (PEC) by SMBus devices is optional for SMBus devices but required for devices participating in and only during the address resolution protocol (ARP) process. The PEC is a CRC-8 error checking byte, calculated on all the message bytes. The PEC is appended to the message by the device that supplied the last data byte.
PAGE 1258
Functional description SMBus timeouts interrupt is driven by SLTF and masked with the IICIE bit. The SLTF bit must be cleared by software by writing 1 to it in the interrupt routine. You can determine the interrupt type by reading the Status Register. NOTE In master receive mode, the FACK bit must be set to zero before the last byte transfer. Table 47-44.
PAGE 1259
Chapter 47 Inter-Integrated Circuit (I2C) 47.4.6.4 Arbitration lost interrupt The I2C is a true multimaster bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. The I2C module asserts the arbitration-lost interrupt when it loses the data arbitration process and the ARBL bit in the Status Register is set.
PAGE 1260
Functional description occurs within the number of clock cycles programmed in this register is ignored by the I2C module. The programmer must specify the size of the glitch (in terms of bus clock cycles) for the filter to absorb and not pass. Noise suppress circuits SCL, SDA internal signals SCL, SDA external signals DFF DFF DFF DFF Figure 47-41. Programmable input glitch filter diagram 47.4.
PAGE 1261
Chapter 47 Inter-Integrated Circuit (I2C) NOTE Before the last byte of master receive mode, TXAK must be set to send a NACK after the last byte’s transfer. Therefore, the DMA must be disabled before the last byte’s transfer. NOTE In 10-bit address mode transmission, the addresses to send occupy 2-3 bytes. During this transfer period, the DMA must be disabled because the C1 register is written to send a repeat start or to change the transfer direction. 47.
PAGE 1262
Initialization/application information Clear IICIF Y Tx Master mode? N Rx Y Tx/Rx? Last byte transmitted? Y Arbitration lost? N Clear ARBL N N Last byte to be read? RXAK=0? N End of address cycle (master Rx)? Y Y (read) 2nd to last byte to be read? Write next byte to Data reg Set TXACK Address transfer see note 1 N Data transfer see note 2 Tx/Rx? N (write) Tx Y Generate stop signal (MST=0) IIAAS=1? Rx SRW=1? N N Y IIAAS=1? Y N Y Y Y Set TX mode ACK from receiver? N Wr
PAGE 1263
Chapter 47 Inter-Integrated Circuit (I2C) Y N SLTF or SHTF2=1? N See typical I2C interrupt routine flow chart FACK=1? Y Clear IICIF Y Tx Master mode? N Rx Y Tx/Rx? Last byte transmitted? Y Last byte to be read? Y N RXAK=0? 2nd to last byte to be read? N Y Y (read) Delay (note 2) Read data from Data reg and soft CRC End of address cycle (master Rx)? N Delay (note 2) Read data and Soft CRC Set TXAK to proper value Delay (note 2) Set TXACK=1 Clear FACK=0 Clear IICIF Write next byte to
PAGE 1264
Initialization/application information K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 1264 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 1265
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The UART allows asynchronous serial communication with peripheral devices and CPUs. 48.1.1 Features The UART includes the following features: • Full-duplex operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.
PAGE 1266
Introduction • 11-bit break character detection option • Independent FIFO structure for transmit and receive • Two receiver wakeup methods: • Idle line wakeup • Address mark wakeup • Address match feature in the receiver to reduce address mark wakeup ISR overhead • Ability to select MSB or LSB to be first bit on wire • Hardware flow control support for request to send (RTS) and clear to send (CTS) signals • Support for ISO 7816 protocol to interface with SIM cards and smart cards • Support for T=0 and T=1
PAGE 1267
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) • Transmitter data buffer at or below watermark • Transmission complete • Receiver data buffer at or above watermark • Idle receiver input • Receiver data buffer overrun • Receiver data buffer underflow • Transmit data buffer overflow • Noise error • Framing error • Parity error • Active edge on receive pin • LIN break detect • Receiver framing error detection • Hardware parity generation and checking • 1/16 bit-time noise detection • DMA interf
PAGE 1268
UART signal descriptions 48.1.2.2 Wait mode UART operation in the Wait mode depends on the state of the C1[UARTSWAI] field. • If C1[UARTSWAI] is cleared, and the CPU is in Wait mode, the UART operates normally. • If C1[UARTSWAI] is set, and the CPU is in Wait mode, the UART clock generation ceases and the UART module enters a power conservation state. C1[UARTSWAI] does not initiate any power down or power up procedures for the ISO-7816 smartcard interface.
PAGE 1269
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.2.1 Detailed signal descriptions The detailed signal descriptions of the UART are shown in the following table. Table 48-2. UART—Detailed signal descriptions Signal I/O Description CTS I Clear to send. Indicates whether the UART can start transmitting data when flow control is enabled. State meaning Asserted—Data transmission can start. Negated—Data transmission cannot start. Timing Assertion—When transmitting device's RTS asserts.
PAGE 1270
Memory map and registers 48.3 Memory map and registers This section provides a detailed description of all memory and registers. Accessing reserved addresses within the memory map results in a transfer error. None of the contents of the implemented addresses are modified as a result of that access. Only byte accesses are supported.
PAGE 1271
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_A015 UART FIFO Receive Watermark (UART0_RWFIFO) 8 R/W 01h 48.3.21/ 1302 4006_A016 UART FIFO Receive Count (UART0_RCFIFO) 8 R 00h 48.3.22/ 1303 4006_A018 UART 7816 Control Register (UART0_C7816) 8 R/W 00h 48.3.23/ 1303 4006_A019 UART 7816 Interrupt Enable Register (UART0_IE7816) 8 R/W 00h 48.3.
PAGE 1272
Memory map and registers UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_A02C UART CEA709.1-B Status Register (UART0_S4) 8 R/W 00h 48.3.43/ 1317 4006_A02D UART CEA709.1-B Received Packet Length (UART0_RPL) 8 R 00h 48.3.44/ 1318 4006_A02E UART CEA709.1-B Received Preamble Length (UART0_RPREL) 8 R 00h 48.3.45/ 1319 4006_A02F UART CEA709.1-B Collision Pulse Width (UART0_CPW) 8 R/W 00h 48.3.
PAGE 1273
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_B015 UART FIFO Receive Watermark (UART1_RWFIFO) 8 R/W 01h 48.3.21/ 1302 4006_B016 UART FIFO Receive Count (UART1_RCFIFO) 8 R 00h 48.3.22/ 1303 4006_B018 UART 7816 Control Register (UART1_C7816) 8 R/W 00h 48.3.23/ 1303 4006_B019 UART 7816 Interrupt Enable Register (UART1_IE7816) 8 R/W 00h 48.3.
PAGE 1274
Memory map and registers UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_B02C UART CEA709.1-B Status Register (UART1_S4) 8 R/W 00h 48.3.43/ 1317 4006_B02D UART CEA709.1-B Received Packet Length (UART1_RPL) 8 R 00h 48.3.44/ 1318 4006_B02E UART CEA709.1-B Received Preamble Length (UART1_RPREL) 8 R 00h 48.3.45/ 1319 4006_B02F UART CEA709.1-B Collision Pulse Width (UART1_CPW) 8 R/W 00h 48.3.
PAGE 1275
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_C015 UART FIFO Receive Watermark (UART2_RWFIFO) 8 R/W 01h 48.3.21/ 1302 4006_C016 UART FIFO Receive Count (UART2_RCFIFO) 8 R 00h 48.3.22/ 1303 4006_C018 UART 7816 Control Register (UART2_C7816) 8 R/W 00h 48.3.23/ 1303 4006_C019 UART 7816 Interrupt Enable Register (UART2_IE7816) 8 R/W 00h 48.3.
PAGE 1276
Memory map and registers UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_C02C UART CEA709.1-B Status Register (UART2_S4) 8 R/W 00h 48.3.43/ 1317 4006_C02D UART CEA709.1-B Received Packet Length (UART2_RPL) 8 R 00h 48.3.44/ 1318 8 R 00h 48.3.45/ 1319 8 R/W 00h 48.3.46/ 1319 4006_C02E UART CEA709.1-B Received Preamble Length (UART2_RPREL) 4006_C02F UART CEA709.
PAGE 1277
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_D015 UART FIFO Receive Watermark (UART3_RWFIFO) 8 R/W 01h 48.3.21/ 1302 4006_D016 UART FIFO Receive Count (UART3_RCFIFO) 8 R 00h 48.3.22/ 1303 4006_D018 UART 7816 Control Register (UART3_C7816) 8 R/W 00h 48.3.23/ 1303 4006_D019 UART 7816 Interrupt Enable Register (UART3_IE7816) 8 R/W 00h 48.3.
PAGE 1278
Memory map and registers UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_D02C UART CEA709.1-B Status Register (UART3_S4) 8 R/W 00h 48.3.43/ 1317 4006_D02D UART CEA709.1-B Received Packet Length (UART3_RPL) 8 R 00h 48.3.44/ 1318 8 R 00h 48.3.45/ 1319 8 R/W 00h 48.3.46/ 1319 4006_D02E UART CEA709.1-B Received Preamble Length (UART3_RPREL) 4006_D02F UART CEA709.
PAGE 1279
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UART memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 400E_A015 UART FIFO Receive Watermark (UART4_RWFIFO) 8 R/W 01h 48.3.21/ 1302 400E_A016 UART FIFO Receive Count (UART4_RCFIFO) 8 R 00h 48.3.22/ 1303 400E_A018 UART 7816 Control Register (UART4_C7816) 8 R/W 00h 48.3.23/ 1303 400E_A019 UART 7816 Interrupt Enable Register (UART4_IE7816) 8 R/W 00h 48.3.
PAGE 1280
Memory map and registers UART memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 400E_A02C UART CEA709.1-B Status Register (UART4_S4) 8 R/W 00h 48.3.43/ 1317 400E_A02D UART CEA709.1-B Received Packet Length (UART4_RPL) 8 R 00h 48.3.44/ 1318 8 R 00h 48.3.45/ 1319 8 R/W 00h 48.3.46/ 1319 400E_A02E UART CEA709.1-B Received Preamble Length (UART4_RPREL) 400E_A02F UART CEA709.
PAGE 1281
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_BDH field descriptions (continued) Field Description 0 1 5 Reserved 4–0 SBR Hardware interrupts from RXEDGIF disabled using polling. RXEDGIF interrupt request enabled. This field is reserved. This read-only field is reserved and always has the value 0. UART Baud Rate Bits The baud rate for the UART is determined by the 13 SBR fields. See Baud rate generation for details.
PAGE 1282
Memory map and registers 48.3.3 UART Control Register 1 (UARTx_C1) This read/write register controls various optional features of the UART system. Address: Base address + 2h offset Bit Read Write Reset 7 6 5 4 3 2 1 0 LOOPS UARTSWAI RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 UARTx_C1 field descriptions Field 7 LOOPS Description Loop Mode Select When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally connected to the receiver input.
PAGE 1283
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C1 field descriptions (continued) Field Description NOTE: 0 1 1 PE • In case the UART is programmed with ILT = 1, a logic of 1'b0 is automatically shifted after a received stop bit, therefore resetting the idle count. • In case the UART is programmed for IDLE line wakeup (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting logic 1s as idle character bits.
PAGE 1284
Memory map and registers UARTx_C2 field descriptions (continued) Field 6 TCIE Description Transmission Complete Interrupt Enable Enables the transmission complete flag, S1[TC], to generate interrupt requests . 0 1 5 RIE Enables S1[RDRF] to generate interrupt requests or DMA transfer requests, based on the state of C5[RDMAS]. Enables the idle line flag, S1[IDLE], to generate interrupt requests , based on the state of C5[ILDMAS]. Enables the UART transmitter.
PAGE 1285
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C2 field descriptions (continued) Field Description transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10, 11, or 12 bits, or 13 or 14 bits). • 10, 11, or 12 logic 0s if S2[BRK13] is cleared • 13 or 14 logic 0s if S2[BRK13] is set. Transmitting break charactersThis field must be cleared when C7816[ISO_7816E] is set. 0 1 Normal transmitter operation. Queue break characters to be sent. 48.3.
PAGE 1286
Memory map and registers UARTx_S1 field descriptions Field 7 TDRE Description Transmit Data Register Empty Flag TDRE will set when the number of datawords in the transmit buffer (D and C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A character that is in the process of being transmitted is not included in the count. To clear TDRE, read S1 when TDRE is set and then write to the UART data register (D).
PAGE 1287
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_S1 field descriptions (continued) Field Description 0 1 3 OR Receiver Overrun Flag OR is set when software fails to prevent the receive data register from overflowing with data. The OR bit is set immediately after the stop bit has been completely received for the dataword that overflows the buffer and all the other error flags (FE, NF, and PF) are prevented from setting.
PAGE 1288
Memory map and registers UARTx_S1 field descriptions (continued) Field Description 48.3.6 UART Status Register 2 (UARTx_S2) The S2 register provides inputs to the MCU for generation of UART interrupts or DMA requests. Also, this register can be polled by the MCU to check the status of these bits. This register can be read or written at any time, with the exception of the MSBF and RXINV bits, which should be changed by the user only between transmit and receive packets.
PAGE 1289
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_S2 field descriptions (continued) Field Description 0 1 4 RXINV LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE].
PAGE 1290
Memory map and registers UARTx_S2 field descriptions (continued) Field Description NOTE: In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible to configure the guard time to 12. However, if a NACK is required to be transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a inactive buffer. Therefore, in this situation, the RAF may deassert one ETU prior to actually being inactive. 0 1 UART receiver idle/inactive waiting for a start bit.
PAGE 1291
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C3 field descriptions (continued) Field Description Setting this field reverses the polarity of the transmitted data output. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity.
PAGE 1292
Memory map and registers the ED register needs to be read, prior to the D register, only if the additional flag data for the dataword needs to be captured. • In the normal 8-bit mode (M bit cleared) if the parity is enabled, you get seven data bits and one parity bit. That one parity bit is loaded into the D register. So, for the data bits, mask off the parity bit from the value you read out of this register.
PAGE 1293
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.3.10 UART Match Address Registers 2 (UARTx_MA2) These registers can be read and written at anytime. The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4[MAEN] field is set. If a match occurs, the following data is transferred to the data register. If a match fails, the following data is discarded.
PAGE 1294
Memory map and registers UARTx_C4 field descriptions (continued) Field 5 M10 Description 10-bit Mode select Causes a tenth, non-memory mapped bit to be part of the serial transmission. This tenth bit is generated and interpreted as a parity bit. The M10 field does not affect the LIN send or detect break behavior. If M10 is set, then both C1[M] and C1[PE] must also be set. This field must be cleared when C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
PAGE 1295
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_C5 field descriptions (continued) Field Description 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. 1 4–0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 48.3.
PAGE 1296
Memory map and registers 48.3.14 UART Modem Register (UARTx_MODEM) The MODEM register controls options for setting the modem configuration. NOTE RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is enabled. This will cause the RTS to deassert during ISO-7816 wait times. The ISO-7816 protocol does not use the RTS and CTS signals.
PAGE 1297
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_MODEM field descriptions (continued) Field Description 0 1 CTS has no effect on the transmitter. Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted.
PAGE 1298
Memory map and registers 48.3.16 UART FIFO Parameters (UARTx_PFIFO) This register provides the ability for the programmer to turn on and off FIFO functionality. It also provides the size of the FIFO that has been implemented. This register may be read at any time. This register must be written only when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is empty.
PAGE 1299
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_PFIFO field descriptions (continued) Field Description When this field is set, the built in FIFO structure for the receive buffer is enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field. If this field is not set, the receive buffer operates as a FIFO of depth one dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared prior to changing this field.
PAGE 1300
Memory map and registers UARTx_CFIFO field descriptions (continued) Field 6 RXFLUSH Description Receive FIFO/Buffer Flush Writing to this field causes all data that is stored in the receive FIFO/buffer to be flushed. This does not affect data that is in the receive shift register. 0 1 5–3 Reserved 2 RXOFE This field is reserved. This read-only field is reserved and always has the value 0. Receive FIFO Overflow Interrupt Enable When this field is set, the RXOF flag generates an interrupt to the host.
PAGE 1301
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_SFIFO field descriptions (continued) Field Description 0 1 6 RXEMPT Receive Buffer/FIFO Empty Asserts when there is no data in the receive FIFO/Buffer. This field does not take into account data that is in the receive shift register. 0 1 5–3 Reserved 2 RXOF Receiver Buffer Overflow Flag Indicates that more data has been written to the receive buffer than it can hold. This field will assert regardless of the value of CFIFO[RXOFE].
PAGE 1302
Memory map and registers UARTx_TWFIFO field descriptions Field 7–0 TXWATER Description Transmit Watermark When the number of datawords in the transmit FIFO/buffer is equal to or less than the value in this register field, an interrupt via S1[TDRE] or a DMA request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For proper operation, the value in TXWATER must be set to be less than the size of the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE]. 48.3.
PAGE 1303
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_RWFIFO field descriptions Field 7–0 RXWATER Description Receive Watermark When the number of datawords in the receive FIFO/buffer is equal to or greater than the value in this register field, an interrupt via S1[RDRF] or a DMA request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE].
PAGE 1304
Memory map and registers UARTx_C7816 field descriptions Field 7–5 Reserved 4 ONACK Description This field is reserved. This read-only field is reserved and always has the value 0. Generate NACK on Overflow When this field is set, the receiver automatically generates a NACK response if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems, this results in the transmitter resending the packet that overflowed until the retransmit threshold for that transmitter is reached.
PAGE 1305
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.3.24 UART 7816 Interrupt Enable Register (UARTx_IE7816) The IE7816 register controls which flags result in an interrupt being issued. This register is specific to 7816 functionality, the corresponding flags that drive the interrupts are not asserted when 7816E is not set/enabled. However, these flags may remain set if they are asserted while 7816E was set and not subsequently cleared. This register may be read or written to at any time.
PAGE 1306
Memory map and registers 48.3.25 UART 7816 Interrupt Status Register (UARTx_IS7816) The IS7816 register provides a mechanism to read and clear the interrupt flags. All flags/ interrupts are cleared by writing a 1 to the field location. Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only the flag condition that occurred since the last time the bit was cleared, not that the condition currently exists.
PAGE 1307
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_IS7816 field descriptions (continued) Field Description 0 1 3 Reserved 2 GTV This field is reserved. This read-only field is reserved and always has the value 0. Guard Timer Violated Interrupt Indicates that one or more of the character guard time, block guard time, or guard time are violated. This interrupt is cleared by writing 1. 0 1 1 TXT A guard time (GT, CGT, or BGT) has not been violated.
PAGE 1308
Memory map and registers UARTx_WP7816T0 field descriptions Field 7–0 WI Description Wait Timer Interrupt (C7816[TTYPE] = 0) Used to calculate the value used for the WT counter. It represents a value between 1 and 255. The value of zero is not valid. This value is used only when C7816[TTYPE] = 0. See . Wait time and guard time parameters 48.3.27 UART 7816 Wait Parameter Register (UARTx_WP7816T1) The WP7816 register contains constants used in the generation of various wait timer counters.
PAGE 1309
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_WN7816 field descriptions Field 7–0 GTN Description Guard Band N Defines a parameter used in the calculation of GT, CGT, and BGT counters. The value represents an integer number between 0 and 255. See Wait time and guard time parameters . 48.3.29 UART 7816 Wait FD Register (UARTx_WF7816) The WF7816 contains parameters that are used in the generation of various counters including GT, CGT, BGT, WT, and BWT.
PAGE 1310
Memory map and registers UARTx_ET7816 field descriptions (continued) Field Description C7816[TTYPE] = 0 and C7816[ANACK] = 1. The value read from this field represents the number of consecutive NACKs that have been received since the last successful transmission. This counter saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are received, the UART continues to retransmit indefinitely. This flag only asserts when C7816[TTYPE] = 0.
PAGE 1311
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.3.32 UART CEA709.1-B Control Register 6 (UARTx_C6) Address: Base address + 21h offset Bit Read Write Reset 7 6 5 4 EN709 TX709 CE CP 0 0 0 0 3 2 1 0 0 0 0 0 0 UARTx_C6 field descriptions Field 7 EN709 Description EN709 Enables the CEA709.1-B feature. 0 1 6 TX709 CEA709.1-B Transmit Enable Starts CEA709.1-B transmission. 0 1 5 CE Enables the collision detect functionality. Collision detect feature is disabled.
PAGE 1312
Memory map and registers UARTx_PCTH field descriptions Field 7–0 PCTH Description Packet Cycle Time Counter High Indicates the most significant byte of maximum period after the line code violation for which the bus could remain idle without decrementing back log count. If the time elapsed after line code violation is greater than packet cycle time, then packet cycle timer expired interrupt is generated.
PAGE 1313
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.3.36 UART CEA709.1-B Secondary Delay Timer High (UARTx_SDTH) Address: Base address + 25h offset Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 SDTH 0 0 0 0 UARTx_SDTH field descriptions Field 7–0 SDTH Description Secondary Delay Timer High This is the most significant byte of the secondary delay timer and is set by software. This is generally a variable value that must be set for each data message to be transmitted.
PAGE 1314
Memory map and registers UARTx_PRE field descriptions Field 7–0 PREAMBLE Description CEA709.1-B Preamble Register The number of bit-sync characters that occur prior to the byte-sync character when preamble is transmitted. NOTE: The minimum preamble length supported by twisted pair wire is four bit-sync fields. 48.3.39 UART CEA709.
PAGE 1315
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_IE field descriptions (continued) Field Description NOTE: This field cannot be cleared except by disabling CEA709. Therefore, ISDIE must be cleared when the first initial sync detection interrupt occurs. If the ISD interrupt is not disabled in the interrupt handler, then user will continuously get interrupts. 0 1 4 PRXIE Packet Received Interrupt Enable Interrupt enable for packet received flag.
PAGE 1316
Memory map and registers UARTx_WB field descriptions (continued) Field Description Size of the basic randomizing window in bit periods after Beta1 time period. 48.3.42 UART CEA709.1-B Status Register (UARTx_S3) Address: Base address + 2Bh offset Bit Read Write Reset 7 6 PEF WBEF 0 0 5 ISD 4 3 2 1 0 PRXF PTXF PCTEF PSF TXFF 0 0 0 0 0 0 UARTx_S3 field descriptions Field 7 PEF Description Preamble Error Flag Indicates that the received preamble has an error.
PAGE 1317
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) UARTx_S3 field descriptions (continued) Field 2 PCTEF Description Packet Cycle Timer Expired Flag Indicates that packet cycle time period has expired with no activity on the line. This flag is cleared by writing 1. 0 1 1 PSF Preamble Start Flag Indicates start of the preamble while the packet is being transmitted. This flag is cleared by writing 1. 0 1 0 TXFF Packet cycle time has not expired. Packet cycle time has expired.
PAGE 1318
Memory map and registers UARTx_S4 field descriptions (continued) Field Description Indicates when the collision occurs during transmission. This flag is cleared by writing 2'b11. If the collision flag is not cleared by software and a valid collision pulse is detected during some other phase of transmission, then collision flag continues to indicate the previous value. 00 01 10 11 1 ILCV Improper Line Code Violation Indicates that line code violation received is not proper.
PAGE 1319
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.3.45 UART CEA709.1-B Received Preamble Length (UARTx_RPREL) Address: Base address + 2Eh offset Bit 7 6 5 4 Read 3 2 1 0 0 0 0 0 RPREL Write Reset 0 0 0 0 UARTx_RPREL field descriptions Field 7–0 RPREL Description Received Preamble Length Indicates the number of bit sync fields received in the preamble. 48.3.46 UART CEA709.
PAGE 1320
Functional description UARTx_RIDT field descriptions Field 7–0 RIDT Description CEA709.1-B Receive IDT register Indicates the indeterminate time period after reception during which any activity on RX line will be discarded. Indeterminate time period value should be less than Beta1 timer value. 48.3.48 UART CEA709.
PAGE 1321
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.1.1 CEA709.1-B packet cycle The following figure illustrates the frame format and Differential Manchester encoding. Differential Manchester encoding requires that each transmitted bit includes a clock transition at the start of the bit period. This allows synchronization with the receiver. 0 1 1 1 1 0 0 1 Transmitter Enable Byte Sync Bit Sync Data+16bit CRC Line Code Beta1 SDT Figure 48-289.
PAGE 1322
Functional description 48.4.1.2 Packet cycle and delay calculations Packet 1 2 Priority slots w 1 2 Packet Randomizing w i ndow Figure 48-291. CEA709.1-B packet cycle Predictive p-persistent CSMA is a technique for collision avoidance that randomizes channel access using knowledge of predicted load. It manages software using data and events reported by the hardware. Beta1 delay is a value set by the software.
PAGE 1323
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) Each node must maintain an estimation of the current channel backlog. Backlog calculation is managed by the layer two software. Initially, the backlog is set to one. The backlog is incremented on transmission by a value indicated in the frames backlog increment field. The backlog decrements under the following conditions: • • • • On waiting to transmit: If Wbase randomizing slots go by without channel activity.
PAGE 1324
Functional description 4. If a single noise event occurs, and it is possible to uniquely identify the noise event, then resynchronization takes place. Starting at sample 15 of the previous time bit period, five data samples are collected. The number and location of the samples are key to decide if an adjustment in time base is required. Table below lists the possible values and the actions associated with each possibility.
PAGE 1325
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) Sample Values (15,16,1,2,3) Action / Event SDDSS In this case, either multiple errors occurred, two or more noise, or two or more noise and a time shift. The most likely case is that samples 16 and 1 are noise. Therefore, no adjustment to time base is made. SDDSD The most likely case is noise for sample 2 and a time shift. Therefore, the time base is sped up by one.
PAGE 1326
Functional description Sample Values (15,16,1,2,3) Action / Event DDSDD It is most likely that sample 1 is noise. Therefore, the time base is sped up by two. Sample 15 becomes sample 1, sample 16 becomes sample 2, sample 1 becomes sample 3, sample 2 becomes sample 4, sample 3 becomes sample 5, and the next sample taken is sample 6. DDDSS In this case multiple errors occurred along with time shift. Therefore, no adjustment to time base is made. DDDSD It is most likely that sample 2 is noise.
PAGE 1327
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. The following table summarizes the results of the preamble verification samples. Table 48-298.
PAGE 1328
Functional description 48.4.1.5 Initial clock synchronization When operating with EN709 set, there are various times when initial clock synchronization is required. When the UART has just been enabled, there is clearly no system clock reference. Additionally, if a channel has remained idle for a significant period of time, such as the arbitration time between packets, substantial clock drift may have occurred in the system between nodes.
PAGE 1329
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 4. If a valid edge is not identified before the delay time expires, and data is queued to be transmitted, the UART considers itself synchronized, and starts the preamble process. 5. If a valid edge is not identified before the delay time expires, and data is not queued to be transmitted, the UART continues attempting to locate a valid edge using the same process, and receives the incoming data packet like in step 3.
PAGE 1330
Functional description preamble completes, the preamble started interrupt is asserted when the UART starts transmitting the preamble. NOTE If the data buffer does not contain at least one byte of valid data and the transmit packet length register has been updated prior to the preamble completing, an underflow event will occur and TXEN is deasserted. The packet is terminated by transmitting line code violation. 48.4.1.
PAGE 1331
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.
PAGE 1332
Functional description 48.4.2.2 Transmission bit order When S2[MSBF] is set, the UART automatically transmits the MSB of the data word as the first bit after the start bit. Similarly, the LSB of the data word is transmitted immediately preceding the parity bit, or the stop bit if parity is not enabled. All necessary bit ordering is handled automatically by the module. Therefore, the format of the data written to D for transmission is completely independent of the S2[MSBF] setting. 48.4.2.
PAGE 1333
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) received. If a NACK is received, the transmitter resends the data, assuming that the number of retries for that character, that is, the number of NACKs received, is less than or equal to the value in ET7816[TXTHRESHOLD]. Hardware supports odd or even parity. When parity is enabled, the bit immediately preceding the stop bit is the parity bit.
PAGE 1334
Functional description As long as C2[SBK] is set, the transmitter logic continuously loads break characters into the transmit shift register. After the software clears C2[SBK], the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. Break bits are not supported when C7816[ISO_7816E] is set/enabled.
PAGE 1335
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.2.6 Hardware flow control The transmitter supports hardware flow control by gating the transmission with the value of CTS. If the clear-to-send operation is enabled, the character is transmitted when CTS is asserted. If CTS is deasserted in the middle of a transmission with characters remaining in the receiver data buffer, the character in the shift register is sent and TXD remains in the mark state until CTS is reasserted.
PAGE 1336
Functional description C1 in transmission TXD data buffer write C1 1 C1 C2 C3 Break C4 C3 C4 Start Stop Break Break C2 C5 C5 CTS_B RTS_B 1. Cn = transmit characters Figure 48-295. Transmitter RTS and CTS timing diagram K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 1336 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 1337
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.3 Receiver INTERNAL BUS BRFA4:0 RE RAF BAUDRATE GENERATOR STOP MODULE CLOCK DATA BUFFER VARIABLE 12-BIT RECEIVE SHIFT REGISTER START SBR12:0 RECEIVE CONTROL M M10 LBKDE MSBF RXINV SHIFT DIRECTION RxD LOOPS RSRC RECEIVER SOURCE CONTROL PE PT From Transmitter RxD PARITY LOGIC WAKEUP LOGIC IRQ / DMA LOGIC ACTIVE EDGE DETECT DMA Requests IRQ Requests To TxD 7816 LOGIC INFRARED LOGIC Figure 48-296.
PAGE 1338
Functional description 48.4.3.2 Receiver bit ordering When S2[MSBF] is set, the receiver operates such that the first bit received after the start bit is the MSB of the dataword. Similarly, the bit received immediately preceding the parity bit, or the stop bit if parity is not enabled, is treated as the LSB for the dataword. All necessary bit ordering is handled automatically by the module. Therefore, the format of the data read from receive data buffer is completely independent of S2[MSBF]. 48.4.3.
PAGE 1339
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) has no stop bit. S1[FE] is set at the same time that received data is placed in the receive data buffer. Framing errors are not supported when C7816[ISO7816E] is set/enabled. However, if S1[FE] is set, data will not be received when C7816[ISO7816E] is set. 48.4.3.5 Receiving break characters The UART recognizes a break character when a start bit is followed by eight, nine, or ten logic 0 data bits and a logic 0 where the stop bit should be.
PAGE 1340
Functional description 48.4.3.6 Hardware flow control To support hardware flow control, the receiver can be programmed to automatically deassert and assert RTS. • RTS remains asserted until the transfer is complete, even if the transmitter is disabled midway through a data transfer. See Transceiver driver enable using RTS for more details.
PAGE 1341
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.3.7 Infrared decoder The infrared decoder converts the received character from the IrDA format to the NRZ format used by the receiver. It also has a 16-RT clock counter that filters noise and indicates when a 1 is received. 48.4.3.7.1 Start bit detection When S2[RXINV] is cleared, the first rising edge of the received character corresponds to the start bit. The infrared decoder resets its counter.
PAGE 1342
Functional description RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic 0. As the receiver samples an incoming frame, it resynchronizes the RT clock on any valid falling edge within the frame. Resynchronization within frames corrects a misalignment between transmitter bit times and receiver bit times. 48.4.3.8.
PAGE 1343
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.3.8.2 Fast data tolerance The following figure shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. IDLE OR NEXT FRAME STOP RT16 RT15 RT14 RT13 RT12 DATA SAMPLES RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK Figure 48-299.
PAGE 1344
Functional description 48.4.3.9.1 Idle input line wakeup (C1[WAKE] = 0) In this wakeup method, an idle condition on the unsynchronized receiver input signal clears C2[RWU] and wakes the UART. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its C2[RWU] and return to the standby state.
PAGE 1345
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.3.9.3 Match address operation Match address operation is enabled when C4[MAEN1] or C4[MAEN2] is set. In this function, a frame received by the RX pin with a logic 1 in the bit position immediately preceding the stop bit is considered an address and is compared with the associated MA1 or MA2 register. The frame is transferred to the receive buffer, and S1[RDRF] is set, only if the comparison matches.
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Functional description UART baud rate = UART module clock / (16 × (SBR[12:0] + BRFD)) The following table lists some examples of achieving target baud rates with a module clock frequency of 10.2 MHz, with and without fractional fine adjustment. Table 48-302. Baud rates (example: module clock = 10.2 MHz) Bits SBR (decimal) Bits BRFA BRFD value Receiver Transmitter Error clock (Hz) Target Baud rate clock (Hz) (%) 17 00000 0 600,000.0 37,500.0 38,400 2.3 16 10011 19/32=0.59375 614,689.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) Table 48-303. Baud rate fine adjust (continued) BRFA Baud Rate Fractional Divisor (BRFD) 10001 17/32 = 0.53125 10010 18/32 = 0.5625 10011 19/32 = 0.59375 10100 20/32 = 0.625 10101 21/32 = 0.65625 10110 22/32 = 0.6875 10111 23/32 = 0.71875 11000 24/32 = 0.75 11001 25/32 = 0.78125 11010 26/32 = 0.8125 11011 27/32 = 0.84375 11100 28/32 = 0.875 11101 29/32 = 0.90625 11110 30/32 = 0.9375 11111 31/32 = 0.96875 48.4.
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Functional description 1. The address bit identifies the frame as an address character. See Receiver wakeup. 48.4.5.2 Nine-bit configuration When C1[M] is set and C4[M10] is cleared, the UART is configured for 9-bit data characters. If C1[PE] is enabled, the ninth bit is either C3[T8/R8] or the internally generated parity bit. This results in a frame consisting of a total of 11 bits.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.5.3 Timing examples Timing examples of these configurations in the NRZ mark/space data format are illustrated in the following figures. The timing examples show all of the configurations in the following sub-sections along with the LSB and MSB first variations. 48.4.5.3.1 Eight-bit format with parity disabled The most significant bit can be used for address mark wakeup.
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Functional description 48.4.5.3.4 Nine-bit format with parity enabled START BIT 0 BIT BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 START BIT 7 PARITY STOP BIT BIT Figure 48-306. Eight bits of data with LSB first and parity START BIT 7 BIT BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 START BIT 0 PARITY STOP BIT BIT Figure 48-307. Eight bits of data with MSB first and parity 48.4.5.3.5 Non-memory mapped tenth bit for parity The most significant memory-mapped bit can be used for address mark wakeup.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) TXD pin driver. Both the transmitter and receiver must be enabled (C2[TE] = 1 and C2[RE] = 1). When C7816[ISO_7816EN] is set, it is not required that both C2[TE] and C2[RE] are set. 48.4.7 Loop operation In loop operation, the transmitter output goes to the receiver input. The unsynchronized receiver input signal is disconnected from the UART. TXINV TRANSMITTER Tx pin output RECEIVER RXD RXINV Figure 48-311.
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Functional description takes to transmit or receive a single bit. For example, a standard 7816 packet, excluding any guard time or NACK elements is 10 ETUs (start bit, 8 data bits, and a parity bit). Guard times and wait times are also measured in ETUs., NOTE The ISO-7816 specification may have certain configuration options that are reserved.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.8.2 Protocol T = 0 When T = 0 protocol is selected, a relatively complex error detection scheme is used. Data characters are formatted as illustrated in the following figure. This scheme is also used for answer to reset and Peripheral Pin Select (PPS) formats.
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Functional description The smallest data unit that is transferred is a block. A block is made up of several data characters and may vary in size depending on the block type. The UART does not provide a mechanism to decode the block type. As part of the block, an LRC or CRC is included. The UART does not calculate the CRC or LRC for transmitted blocks, nor does it verify the validity of the CRC or LRC for received blocks.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) The GT and WT counters reset whenever C7816[TTYPE] = 1 or C7816[ISO_7816E] = 0 or a new dataword start bit has been received or transmitted as specified by the counter descriptions. The CWT, CGT, BWT, BGT counters reset whenever C7816[TTYPE] = 0 or C7816[ISO_7816E] = 0 or a new dataword start bit is received or transmitted as specified by the counter descriptions.
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Functional description 48.4.8.6 UART restrictions in ISO-7816 operation Due to the flexibility of the UART module, there are several features and interrupts that are not supported while running in ISO-7816 mode. These restrictions are documented within the register field definitions. 48.4.9 Infrared interface The UART provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the UART.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.4.9.2 Infrared receive decoder The infrared receive block converts data from the RXD signal to the receive shift register. A narrow pulse is expected for each zero received and no pulse is expected for each one received. A narrow high pulse is expected for a zero bit when S2[RXINV] is cleared, while a narrow low pulse is expected for a zero bit when S2[RXINV] is set.
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System level interrupt sources Table 48-308. UART interrupt sources (continued) Interrupt Source Flag Local enable DMA select Receiver BWT BWTE - Receiver INITD INITDE - Receiver TXT TXTE - Receiver RXT RXTE - Receiver GTV GTVE - 48.6.1 RXEDGIF description S2[RXEDGIF] is set when an active edge is detected on the RxD pin. Therefore, the active edge can be detected only when in two wire mode. A RXEDGIF interrupt is generated only when S2[RXEDGIF] is set.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 48.6.1.3 Exit from low-power modes The receive input active edge detect circuit is still active on low power modes (Wait and Stop). An active edge on the receive input brings the CPU out of low power mode if the interrupt is not masked (S2[RXEDGIF]=1). 48.7 DMA operation In the transmitter, S1[TDRE] can be configured to assert a DMA transfer request. In the receiver, S1[RDRF], can be configured to assert a DMA transfer request.
PAGE 1360
Application information depth of one. This is the default/reset behavior of the module and can be adjusted using the PFIFO[RXFE] and PFIFO[TXFE] bits. Individual watermark levels are also provided for transmit and receive. There are multiple ways to ensure that a data block, which is a set of characters, has completed transmission. These methods include: 1. Set TXFIFO[TXWATER] to 0. TDRE asserts when there is no further data in the transmit buffer.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 6. Write to set up interrupt enable fields desired (C3[ORIE], C3[NEIE], C3[PEIE], and C3[FEIE]) 7. Write to set C4[MAEN1] = 0 and C4[MAEN2] = 0. 8. Write to C5 register and configure DMA control register fields as desired for application. 9. Write to set C7816[INIT] = 1,C7816[ TTYPE] = 0, and C7816[ISO_7816E] = 1. Program C7816[ONACK] and C7816[ANACK] as desired. 10. Write to IE7816 to set interrupt enable parameters as desired. 11.
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Application information 48.8.2.2 Transmission procedure for (C7816[TTYPE] = 1) When the protocol selected is C7816[TTYPE] = 1, data is transferred in blocks. Before starting a transmission, the software must write the size, in number of bytes, for the Information Field portion of the block into TLEN. If a CRC is being transmitted for the block, the value in TLEN must be one more than the size of the information field. The software must then set C2[TE] = 1 and C2[RE] = 1.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) 3. Repeat step 2 for each subsequent transmission. Note During normal operation, S1[TDRE] is set when the shift register is loaded with the next data to be transmitted from the transmit buffer and the number of datawords contained in the transmit buffer is less than or equal to the value in TWFIFO[TXWATER]. This occurs 9/16ths of a bit time after the start of the stop bit of the previous frame.
PAGE 1364
Application information 1. Remove data from the receive data buffer. This could be done by reading data from the data buffer and processing it if the data in the FIFO was still valuable when the overrun event occurred, or using CFIFO[RXFLUSH] to clear the buffer. 2. Clear S1[OR]. Note that if data was cleared using CFIFO[RXFLUSH], then clearing S1[OR] will result in SFIFO[RXUF] asserting. This is because the only way to clear S1[OR] requires reading additional information from the FIFO.
PAGE 1365
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) ET7816[RXTHRESHOLD] value will be incremented by one. However, if sufficient space now exists to write the received data which was NACK'ed, S1[OR] will be blocked and kept from asserting. 48.8.6 Match address registers The two match address registers allow a second match address function for a broadcast or general call address to the serial bus, as an example. 48.8.7 Modem feature This section describes the modem features. 48.8.7.
PAGE 1366
Application information RS-485 TRANSCEIVER UART TRANSMITTER TXD DI RTS_B DE RXD RECEIVER Y DRIVER A RO RE_B Z RECEIVER B Figure 48-315. Transceiver driver enable using RTS In the figure, the receiver enable signal is asserted. Another option for this connection is to connect RTS_B to both DE and RE_B. The transceiver's receiver is disabled while driving. A pullup can pull RXD to a non-floating value during this time.
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Chapter 48 Universal Asynchronous Receiver/Transmitter (UART) If the intent of clearing the interrupt is such that it does not reassert, the interrupt service routine must remove or clear the condition that originally caused the interrupt to assert prior to clearing the interrupt. There are multiple ways that this can be accomplished, including ensuring that an event that results in the wait timer resetting occurs, such as, the transmission of another packet. 48.8.
PAGE 1368
Application information K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 1368 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 1369
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 49.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The I2S (or I2S) module provides a synchronous audio interface (SAI) that supports fullduplex serial interfaces with frame synchronization such as I2S, AC97, TDM, and codec/ DSP interfaces. 49.1.
PAGE 1370
Introduction Figure 49-1. I2S/SAI block diagram 49.1.3 Modes of operation The module operates in these MCU power modes: Run mode, stop modes, and Debug mode. 49.1.3.1 Run mode In Run mode, the SAI transmitter and receiver operate normally. 49.1.3.2 Stop modes In Stop mode, the transmitter is disabled after completing the current transmit frame, and, the receiver is disabled after completing the current receive frame.
PAGE 1371
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 49.1.3.3 Debug mode In Debug mode, the SAI transmitter and/or receiver can continue operating provided the Debug Enable bit is set. When TCSR[DBGE] or RCSR[DBGE] bit is clear and Debug mode is entered, the SAI is disabled after completing the current transmit or receive frame. The transmitter and receiver bit clocks are not affected by Debug mode. 49.
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Memory map and register definition I2S memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_F044 SAI Transmit FIFO Register (I2S0_TFR1) 32 R 0000_0000h 49.3.8/1381 4002_F060 SAI Transmit Mask Register (I2S0_TMR) 32 R/W 0000_0000h 49.3.9/1382 4002_F080 SAI Receive Control Register (I2S0_RCSR) 32 R/W 0000_0000h 49.3.10/ 1383 4002_F084 SAI Receive Configuration 1 Register (I2S0_RCR1) 32 R/W 0000_0000h 49.3.
PAGE 1373
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 49.3.
PAGE 1374
Memory map and register definition I2Sx_TCSR field descriptions (continued) Field Description Enables/disables transmitter operation in Debug mode. The transmit bit clock is not affected by debug mode. 0 1 28 BCE Bit Clock Enable Enables the transmit bit clock, separately from the TE. This field is automatically set whenever TE is set. When software clears this field, the transmit bit clock remains enabled, and this bit remains set, until the end of the current frame.
PAGE 1375
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) I2Sx_TCSR field descriptions (continued) Field Description Indicates that an enabled transmit FIFO is empty. 0 1 16 FRF FIFO Request Flag Indicates that the number of words in an enabled transmit channel FIFO is less than or equal to the transmit FIFO watermark. 0 1 15–13 Reserved 12 WSIE Word Start Interrupt Enable Enables/disables word start interrupts. Enables/disables sync error interrupts.
PAGE 1376
Memory map and register definition I2Sx_TCSR field descriptions (continued) Field Description 0 1 0 FRDE Disables the DMA request. Enables the DMA request. FIFO Request DMA Enable Enables/disables DMA requests. 0 1 Disables the DMA request. Enables the DMA request. 49.3.
PAGE 1377
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) I2Sx_TCR2 field descriptions Field 31–30 SYNC Description Synchronous Mode Configures between asynchronous and synchronous modes of operation. When configured for a synchronous mode of operation, the receiver must be configured for asynchronous operation. 00 01 10 11 29 BCS Asynchronous mode. Synchronous with receiver. Synchronous with another SAI transmitter. Synchronous with another SAI receiver.
PAGE 1378
Memory map and register definition I2Sx_TCR2 field descriptions (continued) Field Description 0 1 23–8 Reserved Bit clock is generated externally in Slave mode. Bit clock is generated internally in Master mode. This field is reserved. This read-only field is reserved and always has the value 0. 7–0 DIV Bit Clock Divide Divides down the audio master clock to generate the bit clock when configured for an internal bit clock. The division value is (DIV + 1) * 2. 49.3.
PAGE 1379
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 49.3.5 SAI Transmit Configuration 4 Register (I2Sx_TCR4) This register must not be altered when TCSR[TE] is set.
PAGE 1380
Memory map and register definition I2Sx_TCR4 field descriptions (continued) Field Description 0 1 0 FSD Frame sync is active high. Frame sync is active low. Frame Sync Direction Configures the direction of the frame sync. 0 1 Frame sync is generated externally in Slave mode. Frame sync is generated internally in Master mode. 49.3.6 SAI Transmit Configuration 5 Register (I2Sx_TCR5) This register must not be altered when TCSR[TE] is set.
PAGE 1381
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 49.3.
PAGE 1382
Memory map and register definition 49.3.9 SAI Transmit Mask Register (I2Sx_TMR) This register is double-buffered and updates: 1. When TCSR[TE] is first set 2. At the end of each frame. This allows the masked words in each frame to change from frame to frame.
PAGE 1383
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 49.3.
PAGE 1384
Memory map and register definition I2Sx_RCSR field descriptions (continued) Field Description Enables/disables receiver operation in Debug mode. The receive bit clock is not affected by Debug mode. 0 1 28 BCE Bit Clock Enable Enables the receive bit clock, separately from RE. This field is automatically set whenever RE is set. When software clears this field, the receive bit clock remains enabled, and this field remains set, until the end of the current frame.
PAGE 1385
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) I2Sx_RCSR field descriptions (continued) Field Description 0 1 16 FRF FIFO Request Flag Indicates that the number of words in an enabled receive channel FIFO is greater than the receive FIFO watermark. 0 1 15–13 Reserved 12 WSIE Word Start Interrupt Enable Enables/disables word start interrupts. Enables/disables sync error interrupts. Enables/disables FIFO error interrupts. Disables the interrupt. Enables the interrupt.
PAGE 1386
Memory map and register definition I2Sx_RCSR field descriptions (continued) Field Description 0 FRDE FIFO Request DMA Enable Enables/disables DMA requests. 0 1 Disables the DMA request. Enables the DMA request. 49.3.
PAGE 1387
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) I2Sx_RCR2 field descriptions (continued) Field Description Configures between asynchronous and synchronous modes of operation. When configured for a synchronous mode of operation, the transmitter must be configured for asynchronous operation. 00 01 10 11 29 BCS Asynchronous mode. Synchronous with transmitter. Synchronous with another SAI receiver. Synchronous with another SAI transmitter.
PAGE 1388
Memory map and register definition I2Sx_RCR2 field descriptions (continued) Field Description 0 1 23–8 Reserved Bit clock is generated externally in Slave mode. Bit clock is generated internally in Master mode. This field is reserved. This read-only field is reserved and always has the value 0. 7–0 DIV Bit Clock Divide Divides down the audio master clock to generate the bit clock when configured for an internal bit clock. The division value is (DIV + 1) * 2. 49.3.
PAGE 1389
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 49.3.14 SAI Receive Configuration 4 Register (I2Sx_RCR4) This register must not be altered when RCSR[RE] is set.
PAGE 1390
Memory map and register definition I2Sx_RCR4 field descriptions (continued) Field Description 0 1 0 FSD Frame sync is active high. Frame sync is active low. Frame Sync Direction Configures the direction of the frame sync. 0 1 Frame Sync is generated externally in Slave mode. Frame Sync is generated internally in Master mode. 49.3.15 SAI Receive Configuration 5 Register (I2Sx_RCR5) This register must not be altered when RCSR[RE] is set.
PAGE 1391
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 49.3.16 SAI Receive Data Register (I2Sx_RDRn) Reading this register introduces one additional peripheral clock wait state on each read.
PAGE 1392
Memory map and register definition 49.3.18 SAI Receive Mask Register (I2Sx_RMR) This register is double-buffered and updates: 1. When RCSR[RE] is first set 2. At the end of each frame This allows the masked words in each frame to change from frame to frame.
PAGE 1393
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) I2Sx_MCR field descriptions Field Description 31 DUF Divider Update Flag Provides the status of on-the-fly updates to the MCLK divider ratio. 0 1 30 MOE MCLK divider ratio is not being updated currently. MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set. MCLK Output Enable Enables the MCLK divider and configures the MCLK signal pin as an output.
PAGE 1394
Functional description I2Sx_MDR field descriptions (continued) Field Description 19–12 FRACT MCLK Fraction 11–0 DIVIDE MCLK Divide Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the DIVIDE field. Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the DIVIDE field. 49.4 Functional description 49.4.
PAGE 1395
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) CLKGEN PLL_OUT ALT_CLK EXTAL SYS_CLK MCLK (other SAIs) MCLK_OUT Fractional Clock Divider 11 10 01 00 1 MCLK_IN SAI MCLK 0 BUS_CLK BCLK_OUT 11 10 01 00 Bit Clock Divider 1 BCLK_IN SAI_CLKMODE SAI_MOE SAI_FRACT/SAI_DIVIDE SAI_MICS 0 BCLK SAI_BCD Figure 49-58. SAI master clock generation 49.4.1.
PAGE 1396
Functional description The SAI receiver includes a software reset that resets all receiver internal logic, including the bit clock generation, status flags and FIFO pointers. It does not reset the configuration registers. The software reset remains asserted until cleared by software. 49.4.2.2 FIFO reset The SAI transmitter includes a FIFO reset that synchronizes the FIFO write pointer to the same value as the FIFO read pointer.
PAGE 1397
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) • In synchronous mode, the transmitter is enabled only when both the receiver and transmitter are both enabled. • It is recommended that the receiver is the last enabled and the first disabled. When operating in synchronous mode, only the bit clock, frame sync, and transmitter/ receiver enable are shared.
PAGE 1398
Data FIFO 49.4.5 Data FIFO 49.4.5.1 Data alignment Each transmit and receive channel includes a FIFO of size 8 × 32-bit. The FIFO data is accessed using the SAI Transmit/Receive Data Registers. Data in the FIFO can be aligned anywhere within the 32-bit wide register through the use of the First Bit Shifted configuration field, which selects the bit index (between 31 and 0) of the first bit shifted.
PAGE 1399
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) 49.4.5.2 FIFO pointers When writing to a TDR, the WFP of the corresponding TFR increments after each valid write. The SAI supports 8-bit, 16-bit and 32-bit writes to the TDR and the FIFO pointer will increment after each individual write. Note that 8-bit writes should only be used when transmitting up to 8-bit data and 16-bit writes should only be used when transmitting up to 16-bit data.
PAGE 1400
Data FIFO 49.4.7.1 FIFO data ready flag The FIFO data ready flag is set based on the number of entries in the FIFO and the FIFO watermark configuration. The transmit data ready flag is set when the number of entries in any of the enabled transmit FIFOs is less than or equal to the transmit FIFO watermark configuration and is cleared when the number of entries in each enabled transmit FIFO is greater than the transmit FIFO watermark configuration.
PAGE 1401
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) The FIFO error flag can generate only an interrupt. 49.4.7.4 Sync error flag The sync error flag, TCSR[SEF] or RCSR[SEF], is set when configured for an externally generated frame sync and the external frame sync asserts when the transmitter or receiver is busy with the previous frame. The external frame sync assertion is ignored and the sync error flag is set.
PAGE 1402
Data FIFO K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012 1402 Preliminary General Business Information Freescale Semiconductor, Inc.
PAGE 1403
Chapter 50 General-Purpose Input/Output (GPIO) 50.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The general-purpose input and output (GPIO) module communicates to the processor core via a zero wait state interface for maximum pin performance. The GPIO registers support 8-bit, 16-bit or 32-bit accesses.
PAGE 1404
Introduction 50.1.2 Modes of operation The following table depicts different modes of operation and the behavior of the GPIO module in these modes. Table 50-1. Modes of operation Modes of operation Description Run The GPIO module operates normally. Wait The GPIO module operates normally. Stop The GPIO module is disabled. Debug The GPIO module operates normally. 50.1.3 GPIO signal descriptions Table 50-2.
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Chapter 50 General-Purpose Input/Output (GPIO) 50.1.3.1 Detailed signal description Table 50-3. GPIO interface-detailed signal descriptions Signal I/O Description PORTA31–PORTA0 I/O General-purpose input/output State meaning PORTB31–PORTB0 Asserted: The pin is logic 1. Deasserted: The pin is logic 0. PORTC31–PORTC0 Timing PORTD31–PORTD0 Assertion: When output, this signal occurs on the risingedge of the system clock.
PAGE 1406
Memory map and register definition GPIO memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 400F_F044 Port Set Output Register (GPIOB_PSOR) 32 W (always 0000_0000h reads 0) 50.2.2/1407 400F_F048 Port Clear Output Register (GPIOB_PCOR) 32 W (always 0000_0000h reads 0) 50.2.3/1408 400F_F04C Port Toggle Output Register (GPIOB_PTOR) 32 W (always 0000_0000h reads 0) 50.2.
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Chapter 50 General-Purpose Input/Output (GPIO) GPIO memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 400F_F110 Port Data Input Register (GPIOE_PDIR) 32 R 0000_0000h 50.2.5/1409 400F_F114 Port Data Direction Register (GPIOE_PDDR) 32 R/W 0000_0000h 50.2.6/1409 50.2.1 Port Data Output Register (GPIOx_PDOR) This register configures the logic levels that are driven on each general-purpose output pins.
PAGE 1408
Memory map and register definition 50.2.3 Port Clear Output Register (GPIOx_PCOR) This register configures whether to clear the fields of PDOR.
PAGE 1409
Chapter 50 General-Purpose Input/Output (GPIO) 50.2.5 Port Data Input Register (GPIOx_PDIR) Address: Base address + 10h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDI R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_PDIR field descriptions Field Description 31–0 PDI Port Data Input Reads 0 at the unimplemented pins for a particular device.
PAGE 1410
Functional description 50.3.1 General-purpose input The logic state of each pin is available via the Port Data Input registers, provided the pin is configured for a digital function and the corresponding Port Control and Interrupt module is enabled. The Port Data Input registers return the synchronized pin state after any enabled digital filter in the Port Control and Interrupt module.
PAGE 1411
Chapter 51 Touch sense input (TSI) 51.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The touch sensing input (TSI) module provides capacitive touch sensing detection with high sensitivity and enhanced robustness. Each TSI pin implements the capacitive measurement of an electrode having individual programmable detection thresholds and result registers.
PAGE 1412
Overview • End-of-scan or out-of-range interrupt • TSI error interrupts: pad short to VDD/VSS or conversion overrun Automatically compensates for temperature and supply voltage variations within operating parameters Stand alone operation not requiring any external crystal even in low-power modes Configurable integration of each electrode capacitance measurement from 1 to 4096 periods Programmable Electrode Oscillator and TSI Reference Oscillator allowing high sensitivity, small scan time, and low-power fun
PAGE 1413
Chapter 51 Touch sense input (TSI) 51.3.1 Electrode capacitance measurement unit The electrode capacitance measurement unit senses the capacitance of a TSI pin and outputs a 16-bit result. This module is based in dual oscillator architecture. One oscillator is connected to the external electrode array and oscillates according to the electrode capacitance, while the other according to an internal reference capacitor.
PAGE 1414
Modes of operation during low-power mode, thereby contributing to smaller average power consumption. The TSI, in low-power mode, has the capability to wake the CPU upon an electrode capacitance change. When the CPU wakes, the TSI enters active mode, and a shorter scan period can provide a faster response time and more robust touch detection. Apart from the periodical mode, the electrode scan unit also allows software triggering of the electrode scans.
PAGE 1415
Chapter 51 Touch sense input (TSI) Table 51-1.
PAGE 1416
Modes of operation capacitance measurements. The scan period is defined by GENCS[LPSCNITV] . Two low-power clock sources are available in the TSI low-power mode, LPOCLK, and VLPOSCCLK, being selected by GENCS[LPCLKS]. In low-power mode, the TSI interrupt can also be configured as end-of-scan or out-ofrange and the GENCS[TSIIEN] must be set in order to generate these interrupts. The TSI interrupt causes the exit of the low-power mode and entrance in the active mode, and the MCU also wakes up.
PAGE 1417
Chapter 51 Touch sense input (TSI) 51.5 TSI signal descriptions The TSI module has up to 16 external pins for touch sensing. The table below itemizes all the TSI external pins. Table 51-2. TSI signal descriptions Signal TSI_IN[15:0] Description I/O TSI capacitive pins. Switchable driver that connects directly to the electrode pins TSI[15:0] can operate as GPIO pins I/O 51.5.
PAGE 1418
Memory map and register definition TSI memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4004_511C Counter Register (TSI0_CNTR15) 32 R 0000_0000h 51.6.5/1426 4004_5120 Low-Power Channel Threshold register (TSI0_THRESHOLD) 32 R/W 0000_0000h 51.6.6/1427 51.6.
PAGE 1419
Chapter 51 Touch sense input (TSI) TSIx_GENCS field descriptions (continued) Field Description 0 1 27–24 LPSCNITV LPOCLK is selected to determine the scan period in low-power mode. VLPOSCCLK is selected to determine the scan period in low-power mode. TSI Low-Power Mode Scan Interval This field can be changed only if the TSI module is disabled (TSIEN bit = 0).
PAGE 1420
Memory map and register definition TSIx_GENCS field descriptions (continued) Field Description 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 18–16 PS 23 times per electrode. 24 times per electrode. 25 times per electrode. 26 times per electrode. 27 times per electrode. 28 times per electrode. 29 times per electrode. 30 times per electrode. 31 times per electrode. 32 times per electrode.
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Chapter 51 Touch sense input (TSI) TSIx_GENCS field descriptions (continued) Field Description 1 indicates a scanning process is in progress. This bit is read-only and changes automatically by the TSI model. 8 SWTS Software Trigger Start 7 TSIEN Touch Sensing Input Module Enable 6 TSIIE Touch Sensing Input Interrupt Module Enable 5 ERIE Error Interrupt Enable Write a 1 to this bit will start a scan sequence and write a 0 to this bit has no effect. 0 1 0 1 Interrupt from TSI is disabled.
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Memory map and register definition 51.6.
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Chapter 51 Touch sense input (TSI) TSIx_SCANC field descriptions (continued) Field Description 1000 1001 1010 1011 1100 1101 1110 1111 15–8 SMOD 18 µA charge current 20 µA charge current 22 µA charge current 24 µA charge current 26 µA charge current 28 µA charge current 30 µA charge current 32 µA charge current Scan Module 00000000 Others Continue Scan. Scan Period Modulus. 7–6 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
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Memory map and register definition 51.6.3 Pin Enable register (TSIx_PEN) Do not change the settings when TSIEN is 1.
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Chapter 51 Touch sense input (TSI) TSIx_PEN field descriptions (continued) Field Description 0 1 The corresponding pin is not used by TSI. The corresponding pin is used by TSI.
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Memory map and register definition TSIx_PEN field descriptions (continued) Field Description 0 1 The corresponding pin is not used by TSI. The corresponding pin is used by TSI. 1 PEN1 Touch Sensing Input Pin Enable Register 1 0 PEN0 Touch Sensing Input Pin Enable Register 0 0 1 0 1 The corresponding pin is not used by TSI. The corresponding pin is used by TSI. The corresponding pin is not used by TSI. The corresponding pin is used by TSI. 51.6.
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Chapter 51 Touch sense input (TSI) 51.6.
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Functional description Figure 51-32. Dual electrode capacitance measurement 51.7.1.1 TSI electrode oscillator The TSI electrode oscillator circuit is illustrated in the following figure. A configurable constant current source is used to charge and discharge the external electrode capacitance. A buffer hysteresis defines the oscillator delta voltage. The delta voltage defines the margins of high and low voltage which are the reference input of the comparator at different times.
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Chapter 51 Touch sense input (TSI) Figure 51-33. TSI electrode oscillator circuit The current source applied to the pad capacitance is controlled by the SCANC[EXTCHRG]. The hysteresis delta voltage is defined inn the module electrical specifications present in the device data sheet.. The figure below shows the voltage amplitude waveform of the electrode capacitance charging and discharging with a programmable current.
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Functional description ΔV: Hysteresis delta voltage By this equation, for example, an electrode with Celec= 20 pF and a current source of I = 16 µA and ΔV = 600 mV has the following oscillation frequency: Felec 16 µA 2 * 20pF * 600mV 0.67MHz Figure 51-36. Equation 2: TSI electrode oscillator frequency The current source is used to accommodate the TSI electrode oscillator frequency with different electrode capacitance sizes. 51.7.1.
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Chapter 51 Touch sense input (TSI) Tcap_samp 2*2*16*20pF*600mV 48µs 16µA 51.7.1.3 TSI reference oscillator The TSI reference oscillator has the same topology of the TSI electrode oscillator. The TSI reference oscillator instead of using an external capacitor for the electrode oscillator has an internal reference capacitor. The TSI reference oscillator has an independent programmable current source controlled by the SCANC[REFCHRG].
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Functional description 51.7.3 Electrode scan unit This section describes the functionality of the electrode scan unit, which is responsible for triggering the start of the active electrode scan. The TSI module needs to periodically scan all active electrodes to determine whether a touch event has occurred. The electrode scan unit is responsible for defining two independent scan periods, one for TSI active mode and the other for TSI low-power mode.
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Chapter 51 Touch sense input (TSI) 51.7.3.2 Scan trigger The scan trigger can be set to periodical scan or software trigger. GENCS[STM] determines the TSI scan trigger mode. If STM = 1, the trigger mode is selected as continuous. If STM = 0, the software trigger mode is selected. In periodic mode, the scan trigger is generated automatically by the electrode scan unit 51.7.3.3 Software trigger mode The software trigger scan is started by writing 1 to the bit GENCS[SWTS].
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Functional description When the electrode scan unit starts a scan sequence, all the active electrodes will be scanned sequentially, with each electrode having a scanned time defined by the GENCS[NSCN]. The counter value is the sum of the total scan times of that electrode. First Active Electrode Scan States ... ... ... Result Counter ... Last Scan 1st Scan 1st Scan Last Active Electrode Second Active Electrode Count from 0 to result Count from 0 to result Last Scan 1st Scan Last Scan ... ...
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Chapter 51 Touch sense input (TSI) 51.7.3.4.4 Over-run interrupt If an electrode scan is in progress and there is a scan trigger, the electrode scan unit generates and over-run error by asserting GENCS[OVRF]. If the TSI error interrupt is active by setting GENCS[ERIE], an interrupt request is asserted. The OVRF flag is cleared by writing 1 to it. 51.7.4 Touch detection unit The touch detection unit is responsible for detecting electrode capacitance changes while in low-power mode.
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Application information 51.8 Application information After enabling the TSI module for the first time, calibrate all the enabled channels by setting proper high and low threshold value for each active channel. All of the channel dedicated counter values can be read from each counter value register, then the software suite can adjust the threshold based on these values. Follow proper PCB layout guidelines for board design on electrode shapes, sizes, routes, etc. Visit www.freescale.
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Chapter 52 JTAG Controller (JTAGC) 52.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration chapter. The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. 52.1.
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Introduction Power-on reset Test Access Port (TAP) Controller TMS TCK 1-bit Bypass Register 32-bit Device Identification Register TDI TDO Boundary Scan Register TAP Instruction Decoder TAP Instruction Register Figure 52-1. JTAG (IEEE 1149.1) block diagram 52.1.2 Features The JTAGC block is compliant with the IEEE 1149.1-2001 standard, and supports the following features: • IEEE 1149.
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Chapter 52 JTAG Controller (JTAGC) 52.1.3.1 Reset The JTAGC block is placed in reset when either power-on reset is asserted, or the TMS input is held high for enough consecutive rising edges of TCK to sequence the TAP controller state machine into the Test-Logic-Reset state. Holding TMS high for five consecutive rising edges of TCK guarantees entry into the Test-Logic-Reset state regardless of the current TAP controller state. Asserting power-on reset results in asynchronous entry into the reset state.
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External signal description 52.2 External signal description The JTAGC consists of a set of signals that connect to off chip development tools and allow access to test support functions. The JTAGC signals are outlined in the following table and described in the following sections. Table 52-1. JTAG signal properties Name I/O Function Reset State Pull TCK Input Test Clock — Down TDI Input Test Data In — TDO Output Test Data Out TMS Input Test Mode Select High Up Z1 — — Up 1.
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Chapter 52 JTAG Controller (JTAGC) 52.3 Register description This section provides a detailed description of the JTAGC block registers accessible through the TAP interface, including data registers and the instruction register. Individual bit-level descriptions and reset states of each register are included. These registers are not memory-mapped and can only be accessed through the TAP. 52.3.1 Instruction register The JTAGC block uses a 4-bit instruction register as shown in the following figure.
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Register description 52.3.3 Device identification register The device identification (JTAG ID) register, shown in the following figure, allows the revision number, part number, manufacturer, and design center responsible for the design of the part to be determined through the TAP. The device identification register is selected for serial data transfer between TDI and TDO when the IDCODE instruction is active.
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Chapter 52 JTAG Controller (JTAGC) scan register cell, as described in the IEEE 1149.1-2001 standard and discussed in Boundary scan. The size of the boundary scan register and bit ordering is devicedependent and can be found in the device BSDL file. 52.4 Functional description This section explains the JTAGC functional description. 52.4.
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Functional description TEST LOGIC RESET 1 0 1 1 1 SELECT-DR-SCAN RUN-TEST/IDLE SELECT-IR-SCAN 0 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-IR SHIFT-DR 0 0 1 1 1 1 EXIT1-IR EXIT1-DR 0 0 PAUSE-DR PAUSE-IR 0 0 1 0 EXIT2-DR 1 0 EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK. Figure 52-4. IEEE 1149.1-2001 TAP controller finite state machine 52.4.3.
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Chapter 52 JTAG Controller (JTAGC) 52.4.3.2 Selecting an IEEE 1149.1-2001 register Access to the JTAGC data registers is achieved by loading the instruction register with any of the JTAGC block instructions while the JTAGC is enabled. Instructions are shifted in via the Select-IR-Scan path and loaded in the Update-IR state. At this point, all data register access is performed via the Select-DR-Scan path.
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Functional description Table 52-3. 4-bit JTAG instructions (continued) Instruction Code[3:0] Instruction Summary ARM JTAG-DP Reserved 1011 This instruction goes the ARM JTAG-DP controller. See the ARM JTAG-DP documentation for more information. CLAMP 1100 Selects bypass register while applying preloaded values to output pins and asserting functional reset ARM JTAG-DP Reserved 1110 This instruction goes the ARM JTAG-DP controller. See the ARM JTAG-DP documentation for more information.
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Chapter 52 JTAG Controller (JTAGC) of the boundary scan register cells on the falling edge of TCK in the Update-DR state. The data is applied to the external output pins by the EXTEST or CLAMP instruction. System operation is not affected. 52.4.4.4 SAMPLE instruction The SAMPLE instruction obtains a sample of the system data and control signals present at the MCU input pins and just before the boundary scan register cells at the output pins.
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Initialization/Application information single bit (the bypass register) while conducting an EXTEST type of instruction through the boundary scan register. CLAMP also asserts the internal system reset for the MCU to force a predictable internal state. 52.4.4.8 BYPASS instruction BYPASS selects the bypass register, creating a single-bit shift register path between TDI and TDO. BYPASS enhances test efficiency by reducing the overall shift path when no test operation of the MCU is required.
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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.