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40.7 Functional description
The CMT module primarily consists of clock divider, carrier generator, and modulator.
40.7.1 Clock divider
The CMT was originally designed to be based on an 8 MHz bus clock that could be
divided by 1, 2, 4, or 8 according to the specification. To be compatible with higher bus
frequency, the primary prescaler (PPS) was developed to receive a higher frequency and
generate a clock enable signal called intermediate frequency (IF). This IF must be
approximately equal to 8 MHz and will work as a clock enable to the secondary
prescaler. The following figure shows the clock divider block diagram.
Primary
prescaler
if_clk_enable
divider_enable
Bus clock
Secondary
prescaler
Figure 40-14. Clock divider block diagram
For compatibility with previous versions of CMT, when bus clock = 8 MHz, the PPS
must be configured to zero. The PPS counter is selected according to the bus clock to
generate an intermediate frequency approximately equal to 8 MHz.
40.7.2 Carrier generator
The carrier generator resolution is 125 ns when operating with an 8 MHz intermediate
frequency signal and the secondary prescaler is set to divide by 1, or, when
MSC[CMTDIV] = 00. The carrier generator can generate signals with periods between
250 ns (4 MHz) and 127.5 μs (7.84 kHz) in steps of 125 ns. The following table shows
the relationship between the clock divide bits and the carrier generator resolution,
minimum carrier generator period, and minimum modulator period.
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1000
Preliminary
Freescale Semiconductor, Inc.
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