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Table 40-19. Clock divider
Bus clock
(MHz)
MSC[CMTDIV]
Carrier generator
resolution (μs)
Min. carrier generator
period
(μs)
Min.
modulator period
(μs)
8 00 0.125 0.25 1.0
8 01 0.25 0.5 2.0
8 10 0.5 1.0 4.0
8 11 1.0 2.0 8.0
The possible duty cycle options depend upon the number of counts required to complete
the carrier period. For example, 1.6 MHz signal has a period of 625 ns and will therefore
require 5 x 125 ns counts to generate. These counts may be split between high and low
times, so the duty cycles available will be:
• 20% with one high and four low times
• 40% with two high and three low times
• 60% with three high and two low times, and
• 80% with four high and one low time
.
For low-frequency signals with large periods, high-resolution duty cycles as a percentage
of the total period, are possible.
The carrier signal is generated by counting a register-selected number of input clocks
(125 ns for an 8 MHz bus) for both the carrier high time and the carrier low time. The
period is determined by the total number of clocks counted. The duty cycle is determined
by the ratio of high-time clocks to total clocks counted. The high and low time values are
user-programmable and are held in two registers.
An alternate set of high/low count values is held in another set of registers to allow the
generation of dual-frequency FSK protocols without CPU intervention.
Note
Only nonzero data values are allowed. The carrier generator
will not work if any of the count values are equal to zero.
MSC[MCGEN] must be set and MSC[BASE] must be cleared to enable carrier generator
clocks. When MSC[BASE] is set, the carrier output to the modulator is held high
continuously. The following figure represents the block diagram of the clock generator.
Chapter 40 Carrier Modulator Transmitter (CMT)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1001
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