Information

Clock and output control
= ?
Secondary High Count Register
Primary High Count Register
8-bit up counter
CLK
CLR
CMTCLK
BASE
FSK
MCGEN
CARRIER OUT (f
cg
)
Secondary Low Count Register
Primary Low Count Register
Primary/
Secondary
Select
= ?
Figure 40-15. Carrier generator block diagram
The high/low time counter is an 8-bit up counter. After each increment, the contents of
the counter are compared with the appropriate high or low count value register. When the
compare value is reached, the counter is reset to a value of 0x01, and the compare is
redirected to the other count value register.
Assuming that the high time count compare register is currently active, a valid compare
will cause the carrier output to be driven low. The counter will continue to increment
starting at the reset value of 0x01. When the value stored in the selected low count value
register is reached, the counter will again be reset and the carrier output will be driven
high.
The cycle repeats, automatically generating a periodic signal which is directed to the
modulator. The lower frequency with maximum period, f
max
, and highest frequency with
minimum period, f
min
, which can be generated, are defined as:
f
max
= f
CMTCLK
÷ (2 * 1) Hz
f
min
= f
CMTCLK
÷ (2 * (2
8
− 1)) Hz
In the general case, the carrier generator output frequency is:
f
cg
= f
CMTCLK
÷ (High count + Low count) Hz
Where: 0 < High count < 256 and
0 < Low count < 256
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1002
Preliminary
Freescale Semiconductor, Inc.
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