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The duty cycle of the carrier signal is controlled by varying the ratio of high time to low
+ high time. As the input clock period is fixed, the duty cycle resolution will be
proportional to the number of counts required to generate the desired carrier period.
40.7.3 Modulator
The modulator block controls the state of the infrared out signal (IRO). The modulator
output is gated on to the IRO signal when the modulator/carrier generator is enabled. .
When the modulator/carrier generator is disabled, the IRO signal is controlled by the state
of the IRO latch. OC[CMTPOL] enables the IRO signal to be active-high or active-low.
The following table describes the functions of the modulators in different modes:
Table 40-20. Mode functions
Mode Function
Time The modulator can gate the carrier onto the modulator output.
Baseband The modulator can control the logic level of the modulator
output.
FSK The modulator can count carrier periods and instruct the
carrier generator to alternate between two carrier frequencies
whenever a modulation period consisting of mark and space
counts, expires.
The modulator provides a simple method to control protocol timing. The modulator has a
minimum resolution of 1.0 μs with an 8 MHz. It can count bus clocks to provide real-
time control, or carrier clocks for self-clocked protocols.
The modulator includes a 17-bit down counter with underflow detection. The counter is
loaded from the 16-bit modulation mark period buffer registers, CMD1 and CMD2. The
most significant bit is loaded with a logic 0 and serves as a sign bit.
When Then
The counter holds a positive value The modulator gate is open and the carrier signal is driven to
the transmitter block.
The counter underflows The modulator gate is closed and a 16-bit comparator is
enabled which compares the logical complement of the value
of the down counter with the contents of the modulation space
period register which has been loaded from the registers,
CMD3 and CMD4.
Chapter 40 Carrier Modulator Transmitter (CMT)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1003
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