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When a match is obtained, the cycle repeats by opening the modulator gate, reloading the
counter with the contents of CMD1 and CMD2, and reloading the modulation space
period register with the contents of CMD3 and CMD4.
The modulation space period is activated when the carrier signal is low to prohibit cutting
off the high pulse of a carrier signal. If the carrier signal is high, the modulator extends
the mark period until the carrier signal becomes low. To deassert the space period and
assert the mark period, the carrier signal must have gone low to ensure that a space period
is not erroneously shortened.
If the contents of the modulation space period register are all zeroes, the match will be
immediate and no space period will be generated, for instance, for FSK protocols that
require successive bursts of different frequencies).
MSC[MCGEN] must be set to enable the modulator timer.
The following figure presents the block diagram of the modulator.
MS bit
16 bits
Mode
Load
FSK
BASE
EXSPC
EOCIE
16 bits
1 6
=?
Counter
Primary/Secondary select
0
1 6
17-bit down counter *
CMTCMD1:CMTCMD2
Clock control
Carrier out (fcg)
Modulator
out
Modulator gate
EOC Flag set
Module interrupt request
System control
CMTCLK
Space period register
CMTCMD3:CMTCMD4
* Denotes hidden register
8
Figure 40-16. Modulator block diagram
40.7.3.1 Time mode
When the modulator operates in Time mode, or, when MSC[MCGEN] is set, and
MSC[BASE] and MSC[FSK] are cleared:
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1004
Preliminary
Freescale Semiconductor, Inc.
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