Information

40.8 CMT interrupts and DMA
The CMT generates an interrupt request or a DMA transfer request according to
MSC[EOCIE], MSC[EOCF], DMA[DMA] bits.
Table 40-23. DMA transfer request x CMT interrupt request
MSC[EOCF] DMA[DMA] MSC[EOCIE] DMA transfer request CMT interrupt request
0 X X 0 0
1 X 0 0 0
1 0 1 0 1
1 1 1 1 0
MSC[EOCF] is set:
• When the modulator is not currently active and MSC[MCGEN] is set to begin the
initial CMT transmission.
• At the end of each modulation cycle when the counter is reloaded from
CMD1:CMD2, while MSC[MCGEN] is set.
When MSC[MCGEN] is cleared and then set before the end of the modulation cycle,
MSC[EOCF] will not be set when MSC[MCGEN] is set, but will become set at the end
of the current modulation cycle.
When MSC[MCGEN] becomes disabled, the CMT module does not set MSC[EOCF] at
the end of the last modulation cycle.
If MSC[EOCIE] is high when MSC[EOCF] is set, the CMT module will generate an
interrupt request or a DMA transfer request.
MSC[EOCF] must be cleared to prevent from being generated by another event like
interrupt or DMA request, after exiting the service routine. See the following table.
Table 40-24. How to clear MSC[EOCF]
DMA[DM
A]
MSC[EOCIE] Description
0 X MSC[EOCF] is cleared by reading MSC followed by an access of CMD2 or CMD4.
1 X MSC[EOCF] is cleared by the CMT DMA transfer done.
The EOC interrupt is coincident with:
Chapter 40 Carrier Modulator Transmitter (CMT)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1009
General Business Information