Information

Signal multiplexing
Module signals
Register
access
16-bit SAR ADC
Peripheral bus
controller 0
Other peripherals
Transfers
Figure 3-31. 16-bit SAR ADC with PGA configuration
Table 3-38. Reference links to related information
Topic Related module Reference
Full description 16-bit SAR ADC with
PGA
16-bit SAR ADC with PGA
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.1.1 ADC instantiation information
This device contains two ADCs. Each ADC contains a PGA channel for a total of two
separate PGAs.
3.7.1.1.1 Number of ADC channels
The number of ADC channels present on the device is determined by the pinout of the
specific device package. For details regarding the number of ADC channel available on a
particular package, refer to the signal multiplexing chapter of this MCU.
3.7.1.2 DMA Support on ADC
Applications may require continuous sampling of the ADC (4K samples/sec) that may
have considerable load on the CPU. Though using PDB to trigger ADC may reduce some
CPU load, The ADC supports DMA request functionality for higher performance when
the ADC is sampled at a very high rate or cases were PDB is bypassed. The ADC can
trigger the DMA (via DMA req) on conversion completion.
Analog
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
102
Preliminary
Freescale Semiconductor, Inc.
General Business Information