Information

41.2.8 RTC Interrupt Enable Register (RTC_IER)
Address: 4003_D000h base + 1Ch offset = 4003_D01Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
Reserved TSIE
Reserved
TAIE TOIE TIIE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
RTC_IER field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–5
Reserved
This field is reserved.
4
TSIE
Time Seconds Interrupt Enable
The seconds interrupt is an edge-sensitive interrupt with a dedicated interrupt vector. It is generated once
a second and requires no software overhead (there is no corresponding status flag to clear).
0 Seconds interrupt is disabled.
1 Seconds interrupt is enabled.
3
Reserved
This field is reserved.
2
TAIE
Time Alarm Interrupt Enable
0 Time alarm flag does not generate an interrupt.
1 Time alarm flag does generate an interrupt.
1
TOIE
Time Overflow Interrupt Enable
0 Time overflow flag does not generate an interrupt.
1 Time overflow flag does generate an interrupt.
0
TIIE
Time Invalid Interrupt Enable
0 Time invalid flag does not generate an interrupt.
1 Time invalid flag does generate an interrupt.
Register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1020
Preliminary
Freescale Semiconductor, Inc.
General Business Information