Information

RTC_WAR field descriptions (continued)
Field Description
0 Writes to the Time Compensation Register are ignored.
1 Writes to the Time Compensation Register complete as normal.
2
TARW
Time Alarm Register Write
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the Time Alarm Register are ignored.
1 Writes to the Time Alarm Register complete as normal.
1
TPRW
Time Prescaler Register Write
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the Time Prescaler Register are ignored.
1 Writes to the Time Prescaler Register complete as normal.
0
TSRW
Time Seconds Register Write
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the Time Seconds Register are ignored.
1 Writes to the Time Seconds Register complete as normal.
41.2.10 RTC Read Access Register (RTC_RAR)
Address: 4003_D000h base + 804h offset = 4003_D804h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
IERR LRR SRR CRR TCRR TARR TPRR TSRR
W
Reset
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RTC_RAR field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
IERR
Interrupt Enable Register Read
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the Interrupt Enable Register are ignored.
1 Reads to the Interrupt Enable Register complete as normal.
6
LRR
Lock Register Read
Table continues on the next page...
Register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1022
Preliminary
Freescale Semiconductor, Inc.
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