Information

RTC_RAR field descriptions (continued)
Field Description
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the Lock Register are ignored.
1 Reads to the Lock Register complete as normal.
5
SRR
Status Register Read
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the Status Register are ignored.
1 Reads to the Status Register complete as normal.
4
CRR
Control Register Read
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the Control Register are ignored.
1 Reads to the Control Register complete as normal.
3
TCRR
Time Compensation Register Read
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the Time Compensation Register are ignored.
1 Reads to the Time Compensation Register complete as normal.
2
TARR
Time Alarm Register Read
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the Time Alarm Register are ignored.
1 Reads to the Time Alarm Register complete as normal.
1
TPRR
Time Prescaler Register Read
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the Time Pprescaler Register are ignored.
1 Reads to the Time Prescaler Register complete as normal.
0
TSRR
Time Seconds Register Read
After being cleared, this bit is set only by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the Time Seconds Register are ignored.
1 Reads to the Time Seconds Register complete as normal.
41.3 Functional description
Chapter 41 Real Time Clock (RTC)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1023
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