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41.3.1.3 Supervisor access

When the supervisor access control bit is clear, only supervisor mode software can write

to the RTC registers, non-supervisor mode software will generate a bus error. Both

supervisor and non-supervisor mode software can always read the RTC registers.

41.3.2 Time counter

The time counter consists of a 32-bit seconds counter that increments once every second

and a 16-bit prescaler register that increments once every 32.768 kHz clock cycle.

The time seconds register and time prescaler register can be written only when SR[TCE]

is clear. Always write to the prescaler register before writing to the seconds register,

because the seconds register increments on the falling edge of bit 14 of the prescaler

The time prescaler register increments provided SR[TCE] is set, SR[TIF] is clear,

SR[TOF] is clear, and the 32.768 kHz clock source is present. After enabling the

oscillator, wait the oscillator startup time before setting SR[TCE] to allow time for the

oscillator clock output to stabilize.

If the time seconds register overflows then the SR[TOF] will set and the time prescaler

The time seconds register and time prescaler register read as zero whenever SR[TOF] is

set.

SR[TIF] is set on VBAT POR and software reset and is cleared by initializing the time

seconds register. The time seconds register and time prescaler register read as zero

whenever SR[TIF] is set.

41.3.3 Compensation

The compensation logic provides an accurate and wide compensation range and can

correct errors as high as 3906 ppm and as low as 0.12 ppm. The compensation factor

must be calculated externally to the RTC and supplied by software to the compensation

although the 1 Hz clock is output to an external pin in support of external calibration

logic.

Chapter 41 Real Time Clock (RTC)

K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012

Freescale Semiconductor, Inc.

Preliminary

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