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Crystal compensation can be supported by using firmware and crystal characteristics to
determine the compensation amount. Temperature compensation can be supported by
firmware that periodically measures the external temperature via ADC and updates the
compensation register based on a look-up table that specifies the change in crystal
frequency over temperature.
The compensation logic alters the number of 32.768 kHz clock cycles it takes for the
prescaler register to overflow and increment the time seconds counter. The time
compensation value is used to adjust the number of clock cycles between -127 and +128.
Cycles are added or subtracted from the prescaler register when the prescaler register
equals 0x3FFF and then increments. The compensation interval is used to adjust the
frequency at which the time compensation value is used, that is, from once a second to
once every 256 seconds.
Updates to the time compensation register will not take effect until the next time the time
seconds register increments and provided the previous compensation interval has expired.
When the compensation interval is set to other than once a second then the compensation
is applied in the first second interval and the remaining second intervals receive no
compensation.
Compensation is disabled by configuring the time compensation register to zero.
41.3.4 Time alarm
The time alarm register, SR[TAF], and IER[TAIE] allow the RTC to generate an
interrupt at a predefined time. The 32-bit time alarm register is compared with the 32-bit
time seconds register each time it increments. The SR[TAF] will set when the time alarm
register equals the time seconds register and the time seconds register increments.
The time alarm flag is cleared by writing the time alarm register. This will usually be the
next alarm value, although writing a value that is less than the time seconds register, such
as zero, will prevent the time alarm flag from setting again. The time alarm flag cannot
otherwise be disabled, although the interrupt it generates is enabled or disabled by
IER[TAIE].
41.3.5 Update mode
The Update Mode bit in the Control register (CR[UM]) configures software write access
to the Time Counter Enable (SR[TCE]) bit. When CR[UM] is clear, SR[TCE] can be
written only when the LR[SRL] bit is set. When CR[UM] is set, the SR[TCE] can also be
written when SR[TCE] is clear or when SR[TIF] or SR[TOF] are set. This allows the
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1026
Preliminary
Freescale Semiconductor, Inc.
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