Information

Connections/Channel Assignment
3.7.1.3.1 ADC0 Connections/Channel Assignment
NOTE
As indicated by the following sections, each ADCx_DPx input
and certain ADCx_DMx inputs may operate as single-ended
ADC channels in single-ended mode.
3.7.1.3.1.1 ADC0 Channel Assignment for 121-Pin Package
ADC Channel
(SC1n[ADCH])
Channel Input signal
(SC1n[DIFF]= 1)
Input signal
(SC1n[DIFF]= 0)
00000 DAD0 ADC0_DP0 and ADC0_DM0
1
ADC0_DP0
2
00001 DAD1 ADC0_DP1 and ADC0_DM1 ADC0_DP1
00010 DAD2 PGA0_DP and PGA0_DM PGA0_DP
00011 DAD3 ADC0_DP3 and ADC0_DM3
3
ADC0_DP3
4
00100
5
AD4a Reserved Reserved
00101
5
AD5a Reserved Reserved
00110
5
AD6a Reserved Reserved
00111
5
AD7a Reserved Reserved
00100
5
AD4b Reserved ADC0_SE4b
00101
5
AD5b Reserved ADC0_SE5b
00110
5
AD6b Reserved ADC0_SE6b
00111
5
AD7b Reserved ADC0_SE7b
01000 AD8 Reserved ADC0_SE8
6
01001 AD9 Reserved ADC0_SE9
7
01010 AD10 Reserved Reserved
01011 AD11 Reserved Reserved
01100 AD12 Reserved ADC0_SE12
01101 AD13 Reserved ADC0_SE13
01110 AD14 Reserved ADC0_SE14
01111 AD15 Reserved ADC0_SE15
10000 AD16 Reserved Reserved
10001 AD17 Reserved ADC0_SE17
10010 AD18 Reserved ADC0_SE18
10011 AD19 Reserved ADC0_DM0
8
10100 AD20 Reserved ADC0_DM1
10101 AD21 Reserved ADC0_SE21
10110 AD22 Reserved ADC0_SE22
Table continues on the next page...
3.7.1.3
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
103
General Business Information