Information
Table 42-5. USB responses to DMA overrun errors (continued)
Errors due to Memory Latency Errors due to Oversized Packets
• For host mode, the TOKDNE interrupt is generated and
the TOK_PID field of the BDT is 1111 to indicate the
DMA latency error. Host mode software can decide to
retry or move to next scheduled item.
• In device mode, the BDT is not written back nor is the
TOKDNE interrupt triggered because it is assumed that
a second attempt is queued and will succeed in the
future.
The packet length field written back to the BDT is the
MaxPacket value that represents the length of the clipped
data actually written to memory.
From here, the software can decide an appropriate course of action for future transactions such as stalling the endpoint,
canceling the transfer, disabling the endpoint, etc.
42.5 Memory map/Register definitions
This section provides the memory map and detailed descriptions of all USB interface
registers.
USB memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_2000 Peripheral ID register (USB0_PERID) 8 R 04h 42.5.1/1041
4007_2004 Peripheral ID Complement register (USB0_IDCOMP) 8 R FBh 42.5.2/1042
4007_2008 Peripheral Revision register (USB0_REV) 8 R 33h 42.5.3/1042
4007_200C Peripheral Additional Info register (USB0_ADDINFO) 8 R 01h 42.5.4/1043
4007_2010 OTG Interrupt Status register (USB0_OTGISTAT) 8 R/W 00h 42.5.5/1043
4007_2014 OTG Interrupt Control Register (USB0_OTGICR) 8 R/W 00h 42.5.6/1044
4007_2018 OTG Status register (USB0_OTGSTAT) 8 R/W 00h 42.5.7/1045
4007_201C OTG Control register (USB0_OTGCTL) 8 R/W 00h 42.5.8/1046
4007_2080 Interrupt Status register (USB0_ISTAT) 8 R/W 00h 42.5.9/1047
4007_2084 Interrupt Enable register (USB0_INTEN) 8 R/W 00h
42.5.10/
1048
4007_2088 Error Interrupt Status register (USB0_ERRSTAT) 8 R/W 00h
42.5.11/
1049
4007_208C Error Interrupt Enable register (USB0_ERREN) 8 R/W 00h
42.5.12/
1050
4007_2090 Status register (USB0_STAT) 8 R 00h
42.5.13/
1051
4007_2094 Control register (USB0_CTL) 8 R/W 00h
42.5.14/
1052
4007_2098 Address register (USB0_ADDR) 8 R/W 00h
42.5.15/
1053
Table continues on the next page...
Chapter 42 Universal Serial Bus OTG Controller (USBOTG)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1039
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