Information

ADC Channel
(SC1n[ADCH])
Channel Input signal
(SC1n[DIFF]= 1)
Input signal
(SC1n[DIFF]= 0)
10111 AD23 Reserved 12-bit DAC0 Output/
ADC0_SE23
11000 AD24 Reserved Reserved
11001 AD25 Reserved Reserved
11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E)
11011 AD27 Bandgap (Diff)
9
Bandgap (S.E)
9
11100 AD28 Reserved Reserved
11101 AD29 -VREFH (Diff) VREFH (S.E)
11110 AD30 Reserved VREFL
11111 AD31 Module Disabled Module Disabled
1. Interleaved with ADC1_DP3 and ADC1_DM3
2. Interleaved with ADC1_DP3
3. Interleaved with ADC1_DP0 and ADC1_DM0
4. Interleaved with ADC1_DP0
5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter
for details.
6. Interleaved with ADC1_SE8
7. Interleaved with ADC1_SE9
8. Interleaved with ADC1_DM3
9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this
ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data
sheet for the bandgap voltage (V
BG
) specification.
3.7.1.3.1.2 ADC0 Channel Assignment for 100-Pin Package
ADC Channel
(SC1n[ADCH])
Channel Input signal
(SC1n[DIFF]= 1)
Input signal
(SC1n[DIFF]= 0)
00000 DAD0 ADC0_DP0 and ADC0_DM0
1
ADC0_DP0
2
00001 DAD1 ADC0_DP1 and ADC0_DM1 ADC0_DP1
00010 DAD2 PGA0_DP and PGA0_DM PGA0_DP
00011 DAD3 ADC0_DP3 and ADC0_DM3
3
ADC0_DP3
4
00100
5
AD4a Reserved Reserved
00101
5
AD5a Reserved Reserved
00110
5
AD6a Reserved Reserved
00111
5
AD7a Reserved Reserved
00100
5
AD4b Reserved ADC0_SE4b
00101
5
AD5b Reserved ADC0_SE5b
00110
5
AD6b Reserved ADC0_SE6b
00111
5
AD7b Reserved ADC0_SE7b
01000 AD8 Reserved ADC0_SE8
6
01001 AD9 Reserved ADC0_SE9
7
01010 AD10 Reserved Reserved
01011 AD11 Reserved Reserved
Table continues on the next page...
Connections/Channel Assignment
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
104
Preliminary
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