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42.9 Hardware Interface
42.9.1
Figure 42-95.
42.10 System Level Issues and Configuration
42.10.1
42.10.2 Power
The USB-FS core is a fully synchronous static design. The power used by the design is
dependant on the application usage of the core. Applications that transfer more data or
cause a greater number of packets to be sent consumes a greater amount of power.
Because the design is synchronous and static, reducing the transitions on the clock net
may conserve power. This may be done in the following ways.
The first is to reduce the clock frequency to the USB module. The clock frequency may
not be reduced below the minimum recommended operating frequency of the USB
module without first disabling the USB operation and disconnecting (via software
disconnect) the USB module from the USB bus.
Alternately, the clock may be shut off to the core to conserve power. Again, this may
only be done after the USB operations on the bus have been disabled and the device has
been disconnected from the USB.
42.10.3 USB Suspend State
USB bus powered devices are required to respond to a 3 ms lack of activity on the USB
bus by going into a suspend state. Software is notified of the suspend condition via the
transition in the port status and control register. Optionally, an interrupt can be generated
that is controlled by the interrupt enable register. In the suspend state, a USB device has a
Chapter 42 Universal Serial Bus OTG Controller (USBOTG)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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