Information

Table 43-5. Signal descriptions
Signal Description I/O
usb_dm USB D– analog data signal. The analog block interfaces directly to the D–
signal on the USB bus.
I/O
usb_dp USB D+ analog data signal. The analog block interfaces directly to the D+
signal on the USB bus.
I/O
avdd33
1
3.3 V regulated analog supply I
avss Analog ground I
dvss Digital ground I
dvdd 1.2 V digital supply I
1. Voltage must be 3.3 V +/- 10% for full functionality of the module. That is, the charger detection function does not work
when this voltage is below 3.0 V, and the CONTROL[START] bit should not be set.
NOTE
The transceiver module also interfaces to the usb_dm and
usb_dp signals. Both modules and the USB host/hub use these
signals as bidirectional, tristate signals.
Information about the signal integrity aspects of the lines including shielding, isolated
return paths, input or output impedance, packaging, suggested external components,
ESD, and other protections can be found in the USB 2.0 specification and in Application
information.
43.4 Memory map/Register definition
This section describes the memory map and registers for the USBDCD module.
USBDCD memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_5000 Control register (USBDCD_CONTROL) 32 R/W 0001_0000h 43.4.1/1076
4003_5004 Clock register (USBDCD_CLOCK) 32 R/W 0000_00C1h 43.4.2/1077
4003_5008 Status register (USBDCD_STATUS) 32 R 0000_0000h 43.4.3/1079
4003_5010 TIMER0 register (USBDCD_TIMER0) 32 R/W 0010_0000h 43.4.4/1080
4003_5014 TIMER1 register (USBDCD_TIMER1) 32 R/W 000A_0028h 43.4.5/1081
4003_5018 TIMER2 register (USBDCD_TIMER2) 32 R/W 0028_0001h 43.4.6/1082
Chapter 43 USB Device Charger Detection Module (USBDCD)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1075
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