Information

43.4.1 Control register (USBDCD_CONTROL)
Contains the control and interrupt bit fields.
Address: 4003_5000h base + 0h offset = 4003_5000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 0
0
0
IE
W
SR
START
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
IF 0 0
W
IACK
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
USBDCD_CONTROL field descriptions
Field Description
31–26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
25
SR
Software Reset
Determines whether a software reset is performed.
0 Do not perform a software reset.
1 Perform a software reset.
24
START
Start Change Detection Sequence
Determines whether the charger detection sequence is initiated.
0 Do not start the sequence. Writes of this value have no effect.
1 Initiate the charger detection sequence. If the sequence is already running, writes of this value have
no effect.
23–17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16
IE
Interrupt Enable
Enables/disables interrupts to the system.
Table continues on the next page...
Memory map/Register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1076
Preliminary
Freescale Semiconductor, Inc.
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