Information

Each individual register is identified by its complete name and the corresponding
mnemonic. The access type can be Supervisor (S) or Unrestricted (U). Most of the
registers can be configured to have either Supervisor or Unrestricted access by
programming the SUPV bit in the MCR Register. These registers are identified as S/U in
the Access column of Table 45-2.
Table 45-2. Module memory map
Register Access Type
Affected by
Hard Reset
Affected by
Soft Reset
Module Configuration Register (MCR) S Yes Yes
Control 1 register (CTRL1) S/U Yes No
Free Running Timer register (TIMER) S/U Yes Yes
Rx Mailboxes Global Mask register (RXMGMASK) S/U No No
Rx Buffer 14 Mask register (RX14MASK) S/U No No
Rx Buffer 15 Mask register (RX15MASK) S/U No No
Error Counter Register (ECR) S/U Yes Yes
Error and Status 1 Register (ESR1) S/U Yes Yes
Interrupt Masks 2 register (IMASK2) S/U Yes Yes
Interrupt Masks 1 register (IMASK1) S/U Yes Yes
Interrupt Flags 2 register (IFLAG2) S/U Yes Yes
Interrupt Flags 1 register (IFLAG1) S/U Yes Yes
Control 2 Register (CTRL2) S/U Yes No
Error and Status 2 Register (ESR2) S/U Yes Yes
Individual Matching Elements Update Register (IMUER) S/U Yes Yes
Lost Rx Frames Register (LRFR) S/U Yes Yes
CRC Register (CRCR) S/U Yes Yes
Rx FIFO Global Mask register (RXFGMASK) S/U No No
Rx FIFO Information Register (RXFIR) S/U No No
Message Buffers S/U No No
Rx Individual Mask Registers S/U No No
The FlexCAN module can store CAN messages for transmission and reception using
Mailboxes and Rx FIFO structures.
This module's memory map includes sixteen 128-bit message buffers (MBs) that occupy
the range from offset 0x80 to 0x17F.
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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