Information

• Each PGA connects to the differential ADC channels
• The PGA outputs differential pairs that are connected to ADC differential input
• When the PGA is used, differential input from the pins is connected to differential
input channel 2 on ADCx
ADC0
DAD1
DAD0
DAD2
DAD3
ADC1
DAD3
DAD2
DAD0
DAD1
PGA1
PGA0
PGA0_DP/ADC0_DP0/ADC1_DP3
PGA0_DM/ADC0_DM0/ADC1_DM3
PGA1_DP/ADC1_DP0/ADC0_DP3
PGA1_DM/ADC1_DM0/ADC0_DM3
ADC1_DP1
ADC1_DM1
ADC0_DP1
ADC0_DM1
Figure 3-34. PGA Integration
3.7.2 CMP Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
111
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