Information

CAN memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_4000 Module Configuration Register (CAN0_MCR) 32 R/W D890_000Fh 45.3.2/1112
4002_4004 Control 1 register (CAN0_CTRL1) 32 R/W 0000_0000h 45.3.3/1117
4002_4008 Free Running Timer (CAN0_TIMER) 32 R/W 0000_0000h 45.3.4/1120
4002_4010 Rx Mailboxes Global Mask Register (CAN0_RXMGMASK) 32 R/W FFFF_FFFFh 45.3.5/1121
4002_4014 Rx 14 Mask register (CAN0_RX14MASK) 32 R/W FFFF_FFFFh 45.3.6/1122
4002_4018 Rx 15 Mask register (CAN0_RX15MASK) 32 R/W FFFF_FFFFh 45.3.7/1123
4002_401C Error Counter (CAN0_ECR) 32 R/W 0000_0000h 45.3.8/1123
4002_4020 Error and Status 1 register (CAN0_ESR1) 32 R/W 0000_0000h 45.3.9/1125
4002_4028 Interrupt Masks 1 register (CAN0_IMASK1) 32 R/W 0000_0000h
45.3.10/
1129
4002_4030 Interrupt Flags 1 register (CAN0_IFLAG1) 32 R/W 0000_0000h
45.3.11/
1130
4002_4034 Control 2 register (CAN0_CTRL2) 32 R/W 00B0_0000h
45.3.12/
1132
4002_4038 Error and Status 2 register (CAN0_ESR2) 32 R/W 0000_0000h
45.3.13/
1135
4002_4044 CRC Register (CAN0_CRCR) 32 R 0000_0000h
45.3.14/
1136
4002_4048 Rx FIFO Global Mask register (CAN0_RXFGMASK) 32 R/W FFFF_FFFFh
45.3.15/
1137
4002_404C Rx FIFO Information Register (CAN0_RXFIR) 32 R Undefined
45.3.16/
1138
4002_4880 Rx Individual Mask Registers (CAN0_RXIMR0) 32 R/W Undefined
45.3.17/
1139
4002_4884 Rx Individual Mask Registers (CAN0_RXIMR1) 32 R/W Undefined
45.3.17/
1139
4002_4888 Rx Individual Mask Registers (CAN0_RXIMR2) 32 R/W Undefined
45.3.17/
1139
4002_488C Rx Individual Mask Registers (CAN0_RXIMR3) 32 R/W Undefined
45.3.17/
1139
4002_4890 Rx Individual Mask Registers (CAN0_RXIMR4) 32 R/W Undefined
45.3.17/
1139
4002_4894 Rx Individual Mask Registers (CAN0_RXIMR5) 32 R/W Undefined
45.3.17/
1139
4002_4898 Rx Individual Mask Registers (CAN0_RXIMR6) 32 R/W Undefined
45.3.17/
1139
4002_489C Rx Individual Mask Registers (CAN0_RXIMR7) 32 R/W Undefined
45.3.17/
1139
4002_48A0 Rx Individual Mask Registers (CAN0_RXIMR8) 32 R/W Undefined
45.3.17/
1139
4002_48A4 Rx Individual Mask Registers (CAN0_RXIMR9) 32 R/W Undefined
45.3.17/
1139
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1110
Preliminary
Freescale Semiconductor, Inc.
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