Information

Address: 4002_4000h base + 8h offset = 4002_4008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TIMER
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_TIMER field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–0
TIMER
Timer Value
Contains the free-running counter value.
45.3.5 Rx Mailboxes Global Mask Register (CANx_RXMGMASK)
This register is located in RAM.
RXMGMASK is provided for legacy application support.
• When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect.
• When the MCR[IRMQ] bit is asserted, RXMGMASK has no effect.
RXMGMASK is used to mask the filter fields of all Rx MBs, excluding MBs 14-15,
which have individual mask registers.
This register can only be written in Freeze mode as it is blocked by hardware in other
modes.
Address: 4002_4000h base + 10h offset = 4002_4010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MG[31:0]
W
Reset
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CANx_RXMGMASK field descriptions
Field Description
31–0
MG[31:0]
Rx Mailboxes Global Mask Bits
These bits mask the Mailbox filter bits. Note that the alignment with the ID word of the Mailbox is not
perfect as the two most significant MG bits affect the fields RTR and IDE, which are located in the Control
and Status word of the Mailbox. The following table shows in detail which MG bits mask each Mailbox filter
field.
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1121
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