Information

CANx_RX14MASK field descriptions (continued)
Field Description
0 The corresponding bit in the filter is "don’t care."
1 The corresponding bit in the filter is checked.
45.3.7 Rx 15 Mask register (CANx_RX15MASK)
This register is located in RAM.
RX15MASK is provided for legacy application support. When the MCR[IRMQ] bit is
asserted, RX15MASK has no effect.
RX15MASK is used to mask the filter fields of Message Buffer 15.
This register can be programmed only while the module is in Freeze mode because it is
blocked by hardware in other modes.
Address: 4002_4000h base + 18h offset = 4002_4018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RX15M[31:0]
W
Reset
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CANx_RX15MASK field descriptions
Field Description
31–0
RX15M[31:0]
Rx Buffer 15 Mask Bits
Each mask bit masks the corresponding Mailbox 15 filter field in the same way that RXMGMASK masks
other Mailboxes' filters. See the description of the CAN_RXMGMASK register.
0 The corresponding bit in the filter is "don’t care."
1 The corresponding bit in the filter is checked.
45.3.8 Error Counter (CANx_ECR)
This register has two 8-bit fields reflecting the value of two FlexCAN error counters:
Transmit Error Counter (TXERRCNT field) and Receive Error Counter (RXERRCNT
field). The rules for increasing and decreasing these counters are described in the CAN
protocol and are completely implemented in the FlexCAN module. Both counters are
read-only except in Freeze mode, where they can be written by the CPU.
FlexCAN responds to any bus state as described in the protocol, for example, transmit
Error Active or Error Passive flag, delay its transmission start time (Error Passive) and
avoid any influence on the bus when in Bus Off state.
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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