Information

The following are the basic rules for FlexCAN bus state transitions:
• If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
128, the FLTCONF field in the Error and Status Register is updated to reflect ‘Error
Passive’ state.
• If the FlexCAN state is ‘Error Passive’, and either TXERRCNT or RXERRCNT
decrements to a value less than or equal to 127 while the other already satisfies this
condition, the FLTCONF field in the Error and Status Register is updated to reflect
‘Error Active’ state.
• If the value of TXERRCNT increases to be greater than 255, the FLTCONF field in
the Error and Status Register is updated to reflect ‘Bus Off’ state, and an interrupt
may be issued. The value of TXERRCNT is then reset to zero.
• If FlexCAN is in ‘Bus Off’ state, then TXERRCNT is cascaded together with another
internal counter to count the 128th occurrences of 11 consecutive recessive bits on
the bus. Hence, TXERRCNT is reset to zero and counts in a manner where the
internal counter counts 11 such bits and then wraps around while incrementing the
TXERRCNT. When TXERRCNT reaches the value of 128, the FLTCONF field in
the Error and Status Register is updated to be ‘Error Active’ and both error counters
are reset to zero. At any instance of dominant bit following a stream of less than 11
consecutive recessive bits, the internal counter resets itself to zero without affecting
the TXERRCNT value.
• If during system start-up, only one node is operating, then its TXERRCNT increases
in each message it is trying to transmit, as a result of acknowledge errors (indicated
by the ACKERR bit in the Error and Status Register). After the transition to ‘Error
Passive’ state, the TXERRCNT does not increment anymore by acknowledge errors.
Therefore the device never goes to the ‘Bus Off’ state.
• If the RXERRCNT increases to a value greater than 127, it is not incremented
further, even if more errors are detected while being a receiver. At the next
successful message reception, the counter is set to a value between 119 and 127 to
resume to ‘Error Active’ state.
Address: 4002_4000h base + 1Ch offset = 4002_401Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RXERRCNT TXERRCNT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_ECR field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–8
RXERRCNT
Receive Error Counter
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1124
Preliminary
Freescale Semiconductor, Inc.
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