Information

CANx_ECR field descriptions (continued)
Field Description
7–0
TXERRCNT
Transmit Error Counter
45.3.9 Error and Status 1 register (CANx_ESR1)
This register reflects various error conditions, some general status of the device and it is
the source of interrupts to the CPU.
The CPU read action clears bits 15-10. Therefore the reported error conditions (bits
15-10) are those that occurred since the last time the CPU read this register. Bits 9-3 are
status bits.
The following table shows the FlexCAN state variables and their meanings. Other
combinations not shown in the table are reserved.
SYNCH IDLE TX RX FlexCAN State
0 0 0 0 Not synchronized to
CAN bus
1 1 x x Idle
1 0 1 0 Transmitting
1 0 0 1 Receiving
Address: 4002_4000h base + 20h offset = 4002_4020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
SYNCH
TWRNINT
RWRNINT
W w1c w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1125
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