Information
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BIT1ERR
BIT0ERR
ACKERR
CRCERR
FRMERR
STFERR
TXWRN
RXWRN
IDLE
TX FLTCONF RX
BOFFINT
ERRINT
WAKINT
W
w1c
w1c
w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_ESR1 field descriptions
Field Description
31–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18
SYNCH
CAN Synchronization Status
This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate
in the communication process. It is set and cleared by the FlexCAN. See the table in the overall
CAN_ESR1 register description.
0 FlexCAN is not synchronized to the CAN bus.
1 FlexCAN is synchronized to the CAN bus.
17
TWRNINT
Tx Warning Interrupt Flag
If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN flag transitions from 0 to
1, meaning that the Tx error counter reached 96. If the corresponding mask bit in the Control Register
(TWRNMSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
WRNEN is negated, this flag is masked. CPU must clear this flag before disabling the bit. Otherwise it will
be set when the WRNEN is set again. Writing 0 has no effect. This flag is not generated during Bus Off
state. This bit is not updated during Freeze mode.
0 No such occurrence.
1 The Tx error counter transitioned from less than 96 to greater than or equal to 96.
16
RWRNINT
Rx Warning Interrupt Flag
If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN flag transitions from 0 to
1, meaning that the Rx error counters reached 96. If the corresponding mask bit in the Control Register
(RWRNMSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
WRNEN is negated, this flag is masked. CPU must clear this flag before disabling the bit. Otherwise it will
be set when the WRNEN is set again. Writing 0 has no effect. This bit is not updated during Freeze mode.
0 No such occurrence.
1 The Rx error counter transitioned from less than 96 to greater than or equal to 96.
15
BIT1ERR
Bit1 Error
This bit indicates when an inconsistency occurs between the transmitted and the received bit in a
message.
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1126
Preliminary
Freescale Semiconductor, Inc.
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