Information

CANx_ESR1 field descriptions (continued)
Field Description
NOTE: This bit is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node
sending a passive error flag that detects dominant bits.
0 No such occurrence.
1 At least one bit sent as recessive is received as dominant.
14
BIT0ERR
Bit0 Error
This bit indicates when an inconsistency occurs between the transmitted and the received bit in a
message.
0 No such occurrence.
1 At least one bit sent as dominant is received as recessive.
13
ACKERR
Acknowledge Error
This bit indicates that an Acknowledge Error has been detected by the transmitter node, that is, a
dominant bit has not been detected during the ACK SLOT.
0 No such occurrence.
1 An ACK error occurred since last read of this register.
12
CRCERR
Cyclic Redundancy Check Error
This bit indicates that a CRC Error has been detected by the receiver node, that is, the calculated CRC is
different from the received.
0 No such occurrence.
1 A CRC error occurred since last read of this register.
11
FRMERR
Form Error
This bit indicates that a Form Error has been detected by the receiver node, that is, a fixed-form bit field
contains at least one illegal bit.
0 No such occurrence.
1 A Form Error occurred since last read of this register.
10
STFERR
Stuffing Error
This bit indicates that a Stuffing Error has been detected.
0 No such occurrence.
1 A Stuffing Error occurred since last read of this register.
9
TXWRN
TX Error Warning
This bit indicates when repetitive errors are occurring during message transmission. This bit is not updated
during Freeze mode.
0 No such occurrence.
1 TXERRCNT is greater than or equal to 96.
8
RXWRN
Rx Error Warning
This bit indicates when repetitive errors are occurring during message reception. This bit is not updated
during Freeze mode.
Table continues on the next page...
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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