Information

CANx_ESR1 field descriptions (continued)
Field Description
This field applies when FlexCAN is in low-power mode:
• Stop mode
When a recessive-to-dominant transition is detected on the CAN bus and if the MCR[WAKMSK] bit is set,
an interrupt is generated to the CPU. This bit is cleared by writing it to 1.
When MCR[SLFWAK] is negated, this flag is masked. The CPU must clear this flag before disabling the
bit. Otherwise it will be set when the SLFWAK is set again. Writing 0 has no effect.
0 No such occurrence.
1 Indicates a recessive to dominant transition was received on the CAN bus.
45.3.10 Interrupt Masks 1 register (CANx_IMASK1)
This register allows any number of a range of the 32 Message Buffer Interrupts to be
enabled or disabled for MB31 to MB0. It contains one interrupt mask bit per buffer,
enabling the CPU to determine which buffer generates an interrupt after a successful
transmission or reception, that is, when the corresponding IFLAG1 bit is set.
Address: 4002_4000h base + 28h offset = 4002_4028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BUFLM
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_IMASK1 field descriptions
Field Description
31–0
BUFLM
Buffer MB
i
Mask
Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB31 to MB0.
NOTE: Setting or clearing a bit in the IMASK1 Register can assert or negate an interrupt request, if the
corresponding IFLAG1 bit is set.
0 The corresponding buffer Interrupt is disabled.
1 The corresponding buffer Interrupt is enabled.
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1129
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