Information

CANx_IFLAG1 field descriptions
Field Description
31–8
BUF31TO8I
Buffer MB
i
Interrupt
Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to MB8.
0 The corresponding buffer has no occurrence of successfully completed transmission or reception.
1 The corresponding buffer has successfully completed transmission or reception.
7
BUF7I
Buffer MB7 Interrupt Or "Rx FIFO Overflow"
When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags the interrupt for MB7.
NOTE: This flag is cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by CPU writes.
The BUF7I flag represents "Rx FIFO Overflow" when MCR[RFEN] is set. In this case, the flag indicates
that a message was lost because the Rx FIFO is full. Note that the flag will not be asserted when the Rx
FIFO is full and the message was captured by a Mailbox.
0 No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO
overflow when MCR[RFEN]=1
1 MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when
MCR[RFEN]=1
6
BUF6I
Buffer MB6 Interrupt Or "Rx FIFO Warning"
When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags the interrupt for MB6.
NOTE: This flag is cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by CPU writes.
The BUF6I flag represents "Rx FIFO Warning" when MCR[RFEN] is set. In this case, the flag indicates
when the number of unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
a new one, meaning that the Rx FIFO is almost full. Note that if the flag is cleared while the number of
unread messages is greater than 4, it does not assert again until the number of unread messages within
the Rx FIFO is decreased to be equal to or less than 4.
0 No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost
full when MCR[RFEN]=1
1 MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when
MCR[RFEN]=1
5
BUF5I
Buffer MB5 Interrupt Or "Frames available in Rx FIFO"
When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags the interrupt for MB5.
NOTE: This flag is cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by CPU writes.
The BUF5I flag represents "Frames available in Rx FIFO" when MCR[RFEN] is set. In this case, the flag
indicates that at least one frame is available to be read from the Rx FIFO.
0 No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s)
available in the Rx FIFO, when MCR[RFEN]=1
1 MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO
when MCR[RFEN]=1
4–0
BUF4TO0I
Buffer MB
i
Interrupt Or "reserved"
When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag the interrupts for MB4 to
MB0.
NOTE: These flags are cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by CPU writes.
The BUF4TO0I flags are reserved when MCR[RFEN] is set.
Table continues on the next page...
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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