Information

CANx_IFLAG1 field descriptions (continued)
Field Description
0 The corresponding buffer has no occurrence of successfully completed transmission or reception
when MCR[RFEN]=0.
1 The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
45.3.12 Control 2 register (CANx_CTRL2)
This register contains control bits for CAN errors, FIFO features, and mode selection.
Address: 4002_4000h base + 34h offset = 4002_4034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
WRMFRZ
RFFN TASD MRP RRS
EACEN
W
Reset
0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_CTRL2 field descriptions
Field Description
31–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28
WRMFRZ
Write-Access To Memory In Freeze Mode
Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit can only be written in
Freeze mode and has no effect out of Freeze mode.
0 Maintain the write access restrictions.
1 Enable unrestricted write access to FlexCAN memory.
27–24
RFFN
Number Of Rx FIFO Filters
This 4-bit field defines the number of Rx FIFO filters, as shown in the following table. The maximum
selectable number of filters is determined by the MCU. This field can only be written in Freeze mode as it
is blocked by hardware in other modes. This field must not be programmed with values that make the
number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of Mailboxes present,
defined by MCR[MAXMB].
NOTE: Each group of eight filters occupies a memory space equivalent to two Message Buffers which
means that the more filters are implemented the less Mailboxes will be available.
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1132
Preliminary
Freescale Semiconductor, Inc.
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