Information

CANx_CTRL2 field descriptions (continued)
Field Description
The optimal arbitration timing is that in which the last MB is scanned right before the first bit of the
Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial clock ratio is high
and the CAN baud rate is low then the arbitration can be delayed and vice-versa.
If TASD is 0 then the arbitration start is not delayed, thus the CPU has less time to configure a Tx MB for
the next arbitration, but more time is reserved for arbitration. On the other hand, if TASD is 24 then the
CPU can configure a Tx MB later and less time is reserved for arbitration.
If too little time is reserved for arbitration the FlexCAN may be not able to find winner MBs in time to
compete with other nodes for the CAN bus. If the arbitration ends too much time before the first bit of
Intermission field then there is a chance that the CPU reconfigures some Tx MBs and the winner MB is not
the best to be transmitted.
The optimal configuration for TASD can be calculated as:
TASD = 25 - {f
CANCLK
× [MAXMB + 3 - (RFEN × 8) - (RFEN × RFFN × 2)] × 2} /
{f
SYS
× [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] × (PRESDIV+1)}
where:
• f
CANCLK
is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in Hz
• f
SYS
is the peripheral clock, in Hz
• MAXMB is the value in CTRL1[MAXMB] field
• RFEN is the value in CTRL1[RFEN] bit
• RFFN is the value in CTRL2[RFFN] field
• PSEG1 is the value in CTRL1[PSEG1] field
• PSEG2 is the value in CTRL1[PSEG2] field
• PROPSEG is the value in CTRL1[PROPSEG] field
• PRESDIV is the value in CTRL1[PRESDIV] field
See Section "Arbitration process" and Section "Protocol Timing" for more details.
NOTE: The recommended value for TASD is 22.
18
MRP
Mailboxes Reception Priority
If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching
continues on the Rx FIFO. This bit can be written only in Freeze mode because it is blocked by hardware
in other modes.
0 Matching starts from Rx FIFO and continues on Mailboxes.
1 Matching starts from Mailboxes and continues on Rx FIFO.
17
RRS
Remote Request Storing
If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the
corresponding Message Buffer in the same fashion of a Data Frame. No automatic Remote Response
Frame will be generated.
If this bit is negated the Remote Request Frame is submitted to a matching process and an automatic
Remote Response Frame is generated if a Message Buffer with CODE=0b1010 is found with the same ID.
This bit can be written only in Freeze mode because it is blocked by hardware in other modes.
0 Remote Response Frame is generated.
1 Remote Request Frame is stored.
16
EACEN
Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1134
Preliminary
Freescale Semiconductor, Inc.
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