Information

CANx_CTRL2 field descriptions (continued)
Field Description
This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes filters with their corresponding
bits in the incoming frame by the matching process. This bit does not affect matching for Rx FIFO. This bit
can be written only in Freeze mode because it is blocked by hardware in other modes.
0 Rx Mailbox filter’s IDE bit is always compared and RTR is never compared despite mask bits.
1 Enables the comparison of both Rx Mailbox filter’s IDE and RTR bit with their corresponding bits within
the incoming frame. Mask bits do apply.
15–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1. The number of the last remaining available mailboxes is defined by the least value between the parameter
NUMBER_OF_MB minus 1 and the MCR[MAXMB] field.
2. If Rx Individual Mask Registers are not enabled then all Rx FIFO filters are affected by the Rx FIFO Global Mask.
45.3.13 Error and Status 2 register (CANx_ESR2)
This register reflects various interrupt flags and some general status.
Address: 4002_4000h base + 38h offset = 4002_4038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 LPTM
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 VPS IMB 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_ESR2 field descriptions
Field Description
31–23
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
22–16
LPTM
Lowest Priority Tx Mailbox
If ESR2[VPS] is asserted, this field indicates the lowest number inactive Mailbox (see the IMB bit
description). If there is no inactive Mailbox then the Mailbox indicated depends on CTRL1[LBUF] bit value.
If CTRL1[LBUF] bit is negated then the Mailbox indicated is the one that has the greatest arbitration value
(see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is asserted then the Mailbox indicated
is the highest number active Tx Mailbox. If a Tx Mailbox is being transmitted it is not considered in LPTM
calculation. If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is updated with its
Mailbox number.
15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
14
VPS
Valid Priority Status
Table continues on the next page...
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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