Information

CANx_ESR2 field descriptions (continued)
Field Description
This bit indicates whether IMB and LPTM contents are currently valid or not. VPS is asserted upon every
complete Tx arbitration process unless the CPU writes to Control and Status word of a Mailbox that has
already been scanned, that is, it is behind Tx Arbitration Pointer, during the Tx arbitration process. If there
is no inactive Mailbox and only one Tx Mailbox that is being transmitted then VPS is not asserted. VPS is
negated upon the start of every Tx arbitration process or upon a write to Control and Status word of any
Mailbox.
NOTE: ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB thatis blocked by
abort mechanism. When MCR[AEN] is asserted, the abort code write in C/S of a MB that is being
transmitted (pending abort), or any write attempt into a Tx MB with IFLAG set is blocked.
0 Contents of IMB and LPTM are invalid.
1 Contents of IMB and LPTM are valid.
13
IMB
Inactive Mailbox
If ESR2[VPS] is asserted, this bit indicates whether there is any inactive Mailbox (CODE field is either
0b1000 or 0b0000). This bit is asserted in the following cases:
• During arbitration, if an LPTM is found and it is inactive.
• If IMB is not asserted and a frame is transmitted successfully.
This bit is cleared in all start of arbitration (see Section "Arbitration process").
NOTE: LPTM mechanism have the following behavior: if an MB is successfully transmitted and
ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and the index
related to the MB just transmitted is loaded into ESR2[LPTM].
0 If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
1 If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the
first one.
12–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
45.3.14 CRC Register (CANx_CRCR)
This register provides information about the CRC of transmitted messages.
Address: 4002_4000h base + 44h offset = 4002_4044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 MBCRC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 TXCRC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1136
Preliminary
Freescale Semiconductor, Inc.
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