Information

Table 45-72. DATA BYTEs validity
DLC Valid DATA BYTEs
0 none
1 DATA BYTE 0
2 DATA BYTE 0-1
3 DATA BYTE 0-2
4 DATA BYTE 0-3
5 DATA BYTE 0-4
6 DATA BYTE 0-5
7 DATA BYTE 0-6
8 DATA BYTE 0-7
45.3.35 Rx FIFO structure
When the MCR[RFEN] bit is set, the memory area from 0x80 to 0xDC (which is
normally occupied by MBs 0 to 5) is used by the reception FIFO engine.
The region 0x80-0x8C contains the output of the FIFO which must be read by the CPU as
a Message Buffer. This output contains the oldest message received and not read yet. The
region 0x90-0xDC is reserved for internal use of the FIFO engine.
An additional memory area, that starts at 0xE0 and may extend up to 0x2DC (normally
occupied by MBs 6 up to 37) depending on the CTRL2[RFFN] field setting, contains the
ID Filter Table (configurable from 8 to 128 table elements) that specifies filtering criteria
for accepting frames into the FIFO.
Out of reset, the ID Filter Table flexible memory area defaults to 0xE0 and only extends
to 0xFC, which corresponds to MBs 6 to 7 for RFFN=0, for backward compatibility with
previous versions of FlexCAN.
The following shows the Rx FIFO data structure.
Table 45-73. Rx FIFO structure
31 28 24 23 22 21 20 19 18 17 16 15 8 7 0
0x80 SRR IDE RTR DLC TIME STAMP
0x84 ID Standard ID Extended
0x88 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3
0x8C Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7
0x90
to
0xDC
Reserved
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
1146
Preliminary
Freescale Semiconductor, Inc.
General Business Information