Information
• The CODE field of the Mailbox is either FULL or OVERRUN and it has already
been serviced (the C/S word was read by the CPU and unlocked as described in
Mailbox lock mechanism)
• The CODE field of the Mailbox is either FULL or OVERRUN and an inactivation
(see Mailbox inactivation) is performed
• The Rx FIFO is not full
The scan order for Mailboxes and Rx FIFO is from the matching element with lowest
number to the higher ones.
The matching winner search for Mailboxes is affected by the MCR[IRMQ] bit. If it is
negated the matching winner is the first matched Mailbox regardless if it is free-to-
receive or not. If it is asserted, the matching winner is selected according to the priority
below:
1. the first free-to-receive matched Mailbox;
2. the last non free-to-receive matched Mailbox.
It is possible to select the priority of scan between Mailboxes and Rx FIFO by the
CTRL2[MRP] bit.
If the selected priority is Rx FIFO first:
• If the Rx FIFO is a matched structure and is free-to-receive then the Rx FIFO is the
matching winner regardless of the scan for Mailboxes
• Otherwise (the Rx FIFO is not a matched structure or is not free-to-receive), then the
matching winner is searched among Mailboxes as described above
If the selected priority is Mailboxes first:
• If a free-to-receive matched Mailbox is found, it is the matching winner regardless
the scan for Rx FIFO
• If no matched Mailbox is found, then the matching winner is searched in the scan for
the Rx FIFO
If both conditions above are not satisfied and a non free-to-receive matched Mailbox is
found then the matching winner determination is conditioned by the MCR[IRMQ] bit:
• If MCR[IRMQ] bit is negated the matching winner is the first matched Mailbox
• If MCR[IRMQ] bit is asserted the matching winner is the Rx FIFO if it is a free-to-
receive matched structure, otherwise the matching winner is the last non free-to-
receive matched Mailbox
See the following table for a summary of matching possibilities.
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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