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3. This is a forbidden condition.
4. Matched in MB “Free” means that the frame matched at least one MB free-to-receive regardless of whether it has matched
MBs non-free-to-receive.
5. Matched in FIFO “None” means that the frame has not matched any filter in FIFO. It is as if the FIFO didn’t exist
(CTRL2[RFEN]=0).
6. Matched in FIFO “NotFull” means that the frame has matched a FIFO filter and has empty slots to receive it.
7. Matched in FIFO “Full” means that the frame has matched a FIFO filter but couldn’t store it because it has no empty slots
to receive it.
If a non-safe Mailbox inactivation (see Mailbox inactivation) occurs during matching
process and the Mailbox inactivated is the temporary matching winner then the temporary
matching winner is invalidated. The matching elements scan is not stopped nor restarted,
it continues normally. The consequence is that the current matching process works as if
the matching elements compared before the inactivation did not exist, therefore a
message may be lost.
Suppose, for example, that the FIFO is disabled, IRMQ is enabled and there are two MBs
with the same ID, and FlexCAN starts receiving messages with that ID. Let us say that
these MBs are the second and the fifth in the array. When the first message arrives, the
matching algorithm will find the first match in MB number 2. The code of this MB is
EMPTY, so the message is stored there. When the second message arrives, the matching
algorithm will find MB number 2 again, but it is not "free-to-receive", so it will keep
looking and find MB number 5 and store the message there. If yet another message with
the same ID arrives, the matching algorithm finds out that there are no matching MBs
that are "free-to-receive", so it decides to overwrite the last matched MB, which is
number 5. In doing so, it sets the CODE field of the MB to indicate OVERRUN.
The ability to match the same ID in more than one MB can be exploited to implement a
reception queue (in addition to the full featured FIFO) to allow more time for the CPU to
service the MBs. By programming more than one MB with the same ID, received
messages will be queued into the MBs. The CPU can examine the Time Stamp field of
the MBs to determine the order in which the messages arrived.
Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN
supports individual masking per MB. Refer to the description of the Rx Individual Mask
Registers (RXIMRx). During the matching algorithm, if a mask bit is asserted, then the
corresponding ID bit is compared. If the mask bit is negated, the corresponding ID bit is
"don't care". Please note that the Individual Mask Registers are implemented in RAM, so
they are not initialized out of reset. Also, they can only be programmed while the module
is in Freeze mode; otherwise, they are blocked by hardware.
FlexCAN also supports an alternate masking scheme with only four mask registers
(RGXMASK, RX14MASK, RX15MASK and RXFGMASK) for backwards
compatibility with legacy applications. This alternate masking scheme is enabled when
the IRMQ bit in the MCR Register is negated.
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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