Information

Note
If the BUSY bit is asserted or if the MB is empty, then reading
the Control and Status word does not lock the MB.
Inactivation takes precedence over locking. If the CPU inactivates a locked Rx MB, then
its lock status is negated and the MB is marked as invalid for the current matching round.
Any pending message on the SMB will not be transferred anymore to the MB. An MB is
unlocked when the CPU reads the Free Running Timer Register (see Section "Free
Running Timer Register (TIMER)"), or the C/S word of another MB.
Lock and unlock mechanisms have the same functionality in both Normal and Freeze
modes.
An unlock during Normal or Freeze mode results in the move-in of the pending message.
However, the move-in is postponed if an unlock occurs during a low power mode (see
Modes of operation) and it will take place only when the module resumes to Normal or
Freeze modes.
45.4.7 Rx FIFO
The receive-only FIFO is enabled by asserting the RFEN bit in the MCR. The reset value
of this bit is zero to maintain software backward compatibility with previous versions of
the module that did not have the FIFO feature. The FIFO is 6-message deep. The memory
region occupied by the FIFO structure (both Message Buffers and FIFO engine) is
described in Rx FIFO structure. The CPU can read the received messages sequentially, in
the order they were received, by repeatedly reading a Message Buffer structure at the
output of the FIFO.
The IFLAG[BUF5I] (Frames available in Rx FIFO) is asserted when there is at least one
frame available to be read from the FIFO. An interrupt is generated if it is enabled by the
corresponding mask bit. Upon receiving the interrupt, the CPU can read the message
(accessing the output of the FIFO as a Message Buffer) and the RXFIR register and then
clear the interrupt. If there are more messages in the FIFO the act of clearing the interrupt
updates the output of the FIFO with the next message and update the RXFIR with the
attributes of that message, reissuing the interrupt to the CPU. Otherwise, the flag remains
negated. The output of the FIFO is only valid whilst the IFLAG[BUF5I] is asserted.
The IFLAG[BUF6I] (Rx FIFO Warning) is asserted when the number of unread
messages within the Rx FIFO is increased to 5 from 4 due to the reception of a new one,
meaning that the Rx FIFO is almost full. The flag remains asserted until the CPU clears
it.
Chapter 45 CAN (FlexCAN)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
1165
General Business Information